Si5381/82 Data Sheet

Multi-DSPLL Wireless Jitter Attenuating Clocks

The Si5381/82

is a wireless multi-PLL, jitter-attenuating clock that leverages Silicon

Labs’ latest fourth-generation DSPLL technology to address the form factor, power, and

performance requirements demanded by radio area network equipment, such as small

cells, baseband units, and distributed antenna systems (DAS). The Si538x is the indus-

try’s first multi-PLL wireless clock generator family capable of replacing discrete, high-

performance, VCXO-based clocks with a fully integrated CMOS IC solution. The

Si5381/82

features a multi-PLL architecture that supports independent timing paths for

JESD wireless clocks with less than 85 fs typical phase jitter as well as Ethernet and oth-

er low-jitter, general-purpose clocks. DSPLL technology also supports free-run and hold-

over operation as well as automatic and hitless input clock switching. This unparalleled

integration reduces power and size without compromising the stringent performance and

reliability demanded in wireless applications.

KEY FEATURES

• Supports simultaneous wireless and

general-purpose clocking in a single

device

• Jitter performance: 85 fs RMS typ (12

kHz–20 MHz)

•

Input frequency range:

• Differential: 8 kHz – 750 MHz

• LVCMOS: 8 kHz – 250 MHz

• Output frequency range:

• JESD204B: 480 kHz - 2.94912 GHz

• Differential: 1 Hz – 712.5 MHz

• LVCMOS: 480 kHz – 250 MHz

Applications

•

Pico cells, small cells

•

Mobile backhaul

• Multiservice Distributed Access Systems (MDAS)

Si5381/82

DSPLL

IN1

IN2

IN3

IN0

OUT6

OUT5

OUT4

OUT0

OUT3

OUT2

OUT1

OUT0A

÷INT

Si5382

NVM

C/SPI

Control/

Status

OSC

Si5381

OUT9A

OUT9

OUT8

OUT7

÷INT

DSPLL

Integrated XO Circuit

silabs.com | Building a more connected world. Preliminary Rev. 0.9

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

1. Feature List

The Si5381/82 highlighted features are listed below.

• Digital frequency synthesis eliminates external VCXO and an-

alog loop filter components

• DSPLL_B

supports high-frequency, wireless clocking. Re-

maining three DSPLLs support general-purposing clocking

• Integrated crystal option (Grade E)

• Input frequency range:

• Differential: 7.68 MHz–750 MHz

• LVCMOS: 10 MHz–250 MHz

• Output frequency range (DSPLL_B):

• Differential: up to 2.94912 GHz

• LVCMOS: up to 250 MHz

• Output frequency range (DSPLL_A/C/D):

• Differential: up to 735 MHz

• LVCMOS: up to 250 MHz

• Excellent jitter performance:

• DSPLL_B: 85 fs typ (12 kHz - 20 MHz)

• DSPLL_A/C/D: 150 fs typ (12 kHz - 20 MHz)

• Phase noise floor: –165 dBc/Hz

• Spur performance: –95 dBc max (relative to a 122.88 MHz

carrier)

• Flexible crosspoints route any input to any output clock

• Configurable outputs:

• Compatible with LVDS, LVPECL, LVCMOS, CML, HCSL

• Programmable signal amplitude

• Adjustable output-output delay: 68 ps/step, ±128 steps

• Independent output supply pins: 3.3, 2.5, or 1.8 V

•

Core voltage:

• VDD = 1.8 V ±5%

• VDDA = 3.3 V ±5%

• Automatic free-run, lock, and holdover modes

• Digitally selectable loop bandwidth: DSPLL_B: 1 Hz to 4 kHz

• Hitless switching between input clocks

• Status monitoring (LOS, OOF, LOL)

•

Serial interface: I

C or SPI in-circuit programmable with non-

volatile OTP memory

•

ClockBuilder

Pro software tool simplifies device configura-

tion

• 4 input, 12 output, 64QFN

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

Si5381/82 Data Sheet

Feature List

silabs.com | Building a more connected world. Preliminary Rev. 0.9 | 2