CHA3396-QDG
Ref. : DSCHA3396-QDG0301 - 27 Oct 20
1/16
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc Mosaic - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-rf.com
27-33.5GHz Medium Power Amplifier
GaAs Monolithic Microwave IC in SMD leadless package
Description
The CHA3396-QDG is a 3 stage monolithic
Medium Power Amplifier, which produces
22dB gain for 19dBm output power.
It is designed for a wide range of
applications, from military to commercial
communication systems.
The circuit is manufactured with a pHEMT
process, 0.25µm gate length, via holes
through the substrate, air bridges and
electron beam gate lithography.
It is supplied in RoHS compliant SMD
package.
Main Features
Output Power & PAE versus Frequency
■ Broadband performances: 27-33.5GHz
■ 19dBm Pout at 1dB compression
■ 22dB gain
■ 30dBm OTOI
■ DC bias: Vd= 4.0V, Id= 155mA
■ 24L-QFN4x4 (QDG)
■ MSL1
Main Electrical Characteristics
Tamb.= +25°C
Symbol
Parameter
Min
Typ
Max
Unit
Freq
Frequency range
27.0
33.5
GHz
Gain
Linear Gain
22
dB
P-1dB
Output Power @1dB comp.
19
dBm
OTOI
3
rd
order Intercept point
30
dBm
10
12
14
16
18
20
22
24
26
28
30
23 24 25 26 27 28 29 30 31 32 33 34
Output power (dBm), PAE (%)
Frequency(GHz)
Psat
P-1dB
PAE sat
UMS
A3667A
YYWWG
UMS
A3667A
YYWWG
UMS
A3688A
YYWWG
UMS
A3667A
YYWWG
UMS
A3667A
YYWWG
UMS
A3688A
YYWWG
UMS
A3396
YYWW
CHA3396-QDG
27-33.5GHz Medium Power Amplifier
Ref. : DSCHA3396-QDG0301 - 27 Oct 20
2/16
Specifications subject to change without notice
Bât. Charmille - Parc Mosaic - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-rf.com
Electrical Characteristics
Tamb.= +25°C, Vd = +4.0V
Symbol
Parameter
Min
Typ
Max
Unit
Freq
Frequency range
27
33.5
GHz
Gain
Linear Gain
22
dB
ΔG
Gain variation in temperature
0.026
dB/°C
G
CTRL
Gain control range
15
dB
OTOI
3
rd
order Intercept point
30
dBm
P
-1dB
Output power @ 1dB compression
19
dBm
Psat
Saturated Output Power
21
dBm
RLin
Input Return Loss
10
dB
RLout
Output Return Loss
13
dB
NF
Noise figure
4.5
dB
Id
Quiescent Drain current
155
mA
Vg
Gate voltage
-0.35
V
These values are representative of onboard measurements as defined on the drawing in
paragraph "Evaluation board".
“Power ON” sequence
1. Ground the device
2. Bias MPA gate voltage at Vg low enough (Typically: Vg -1V)
3. Apply Vds bias voltage (Typically: Vd = 4V)
4. Increase slowly Vgs up to quiescent bias drain current Idq
5. Apply RF signal
“Power OFF” sequence
1. Turn off RF signal
2. Bias MPA gate voltage at Vg low enough (Typically: Vg -1V)
3. Turn Vds bias voltage to 0V
4. Turn Vgs bias voltage to 0V