eGaN® FET DATASHEET
EPC23103
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 1
The ePower
TM
Stage IC Product Family integrates input logic interface, level shifting, bootstrap charging
and gate drive buer circuits along with eGaN output FETs. Integration is implemented using EPC’s
proprietary GaN IC technology. The end result is a Power Stage IC that translates logic level input to
high voltage and high current power output that is smaller in size, easier to manufacture, simpler to
design and more ecient to operate.
EFFICIENT POWER CONVERSION
HAL
Key Parameters
PARAMETER VALUE UNIT
Power Stage Load Current (1 MHz) 15
A
Pulsed current (25°C, T
pulse
= 300 μs) 78
Operating PWM Frequency (Minimum) 5 kHz
Operating PWM Frequency (Maximum) 3 MHz
Absolute Maximum Input Voltage 100
V
Operating Input Voltage Range 80
Nominal Bias Supply Voltage 5
Output Current and PWM Frequency Ratings are specied at ambient temperature of 25°C. See Application Information
section for rating methodologies, test conditions, thermal management techniques and thermal derating curves.
All exposed pads feature wettable anks that allow side wall solder inspection. High voltage and low voltage pads
are separated by 0.6mm spacing to meet IPC rules.
Buck Converter, V
IN
= 48 V, V
OUT
= 12 V, Deadtime = 10 ns, L = 2.2 µH, DCR = 700 µΩ, Top Side Heatsink
attached, Airow = 400 LFM, T
A
= 25°C, using EPC90152 Evaluation Board.
EPC
23104
CYYWWE
123456
Figure 1: Performance Curves
500 kHz
1 MHz
2 MHz
Efficiency (%)
Total Power Loss (W)
I
LOAD
(A)
96
95
94
93
92
91
90
24
20
16
12
8
4
0
0 5 10 15 20 25
EPC23104 – ePower™ Stage IC
V
IN
, 100 V
I
Load
, 15 A
PRELIMINARY
Applications
• Buck, Boost, Buck-Boost Converters
• Half-Bridge, Full Bridge LLC Converters
• Motor Drive Inverter
• Class D Audio Amplier
Features
• Integrated high side and low side eGaN® FET with
internal gate driver and level shifter
• 5 V external bias supply
• 3.3 V or 5 V CMOS input logic levels
• Independent high side and low side control inputs
• Logic lockout commands both FETs o when inputs
are both high at same time
• External resistors to tune SW switching times and
over-voltage spikes above rail and below ground
• Robust level shifter operating for hard and soft
switching conditions
• False trigger immunity from fast switching transients
• Synchronous charging for high side bootstrap supply
• Disable input engages low quiescent current mode
from V
DRV
supply
• Power on reset for low side V
DD
supply
• Power on reset for high side V
Boot
supply
• Active gate pull-down for HS FET and LS FET with loss
of V
DRV
supply
• Thermally enhanced QFN
package with exposed top
for low thermal resistance
from junction to top-side
heatsink
Device Information
PART NUMBER Rated R
DS(on)
for HS and LS FETs at 25 °C QFN Package Size (mm)
EPC23104
11 mΩ + 11 mΩ 3.5 x 5
EPC23104 ePower
TM
Stage IC
Package size: 3.5 x 5 mm
https://l.ead.me/EPC23104
eGaN® FET DATASHEET
EPC23104
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 2
Figure 2: EPC23104 Quad Flat No-Lead (QFN)
Package (Transparent Top View)
EPC23104 Pinout Description
Transparent Top View
1
7
6
5432
13
12
11
10
8
9
Pin Description
1
HS
IN
2
LS
IN
3
SD
4
V
DD
5
V
DRV
6
R
DRV
7
AGND
8
PGND
9
SW
10
V
IN
11
V
PHASE
12
R
BOOT
13
V
BOOT
Pin Pin Name Pin Type Description
1 HS
IN
L
High side PWM logic input, level referenced to AGND. Internal pull-down
resistor is connected between HS
IN
and AGND.
2 LS
IN
L
Low side PWM logic input, level referenced to AGND. Internal pull-down
resistor is connected between LS
IN
and AGND.
3 SD L
V
DD
disable input, level referenced to AGND. Internal V
DD
will be disabled
when SD is pulled up to V
DRV
or external 5 V source. Internal pull-down
resistor is connected between SD and AGND, thereby V
DD
will follow V
DRV
with SD connected to AGND by default.
4 V
DD
S
Internal power supply referenced to AGND, connect a bypass capacitor from
V
DD
to AGND.
5 V
DRV
S
External 5 V nominal power supply referenced to AGND, connect a bypass
capacitor from V
DRV
to AGND.
6 R
DRV
G
Insert resistor between R
DRV
to V
DRV
to control the turn-on slew rate of the
driven low side FET.
7 AGND S
Logic ground. Connect bypass capacitors between operating bias supplies,
V
DRV
and V
DD
, to AGND. Internal IC connection between AGND and PGND. Use
star ground external connection with PGND to system ground.
8 PGND P
Input power supply ground return. Connected to source terminal of internal
low side FET. Connect power loop capacitors from V
IN
to PGND.
9 SW P
Output switching node. Connected to output of half-bridge power stage.
SW pin connects together the source terminal of high side FET and the drain
terminal of the low side FET.
10 V
IN
P
Power bus input. Connected to drain terminal of internal high side FET.
Connect power loop capacitors from V
IN
to PGND or power source terminals
of low side FET.
11 V
PHASE
S
Kelvin connection to SW, the output switching node. The oating bootstrap
power supply, V
BOOT
, is also referenced to V
PHASE
.
12 R
BOOT
G
Insert resistor between R
BOOT
to V
BOOT
to control the turn-on slew rate of the
internal high side FET.
13 V
BOOT
S
Floating bootstrap power supply referenced to V
PHASE
(=SW). Connect an
external bypass capacitor from V
BOOT
to V
PHASE
.
Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust