eGaN® FET DATASHEET
EPC7003
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 1
EPC7003 – Enhancement Mode Power Transistor
V
DS
, 100 V
R
DS(on)
, 30 mΩ max
I
D
, 42 A
95% Pb / 5% Sn Solder
Applications
• Space Applications: DC-DC power, motor
drives, lidar, ion thrusters
• Commercial satellite EPS & avionics
• Deep space probes
• High frequency rad hard DC-DC conversion
• Rad hard motor drives
Benets
• Ultra high eciency
• Ultra low R
DS(on)
, Q
G
, Q
GD
,
Q
OSS
, and 0 Q
RR
• Ultra small footprint
• Light weight
• Total dose
- Rated > 1 Mrad
• Single event
- SEE immunity for LET of 85 MeV/(mg/cm
2
)
with V
DS
up to 100% of rated breakdown
• Neutron
- Maintains pre-rad specication for up to
3 x 10
15
neutrons/cm
2
• Superior radiation and electrical performance vs.
rad hard MOSFETs: smaller, lighter, and
greater radiation hardness
EPC7003 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 1.7 x 1.1 mm
EFFICIENT POWER CONVERSION
HAL
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
V
DS
Drain-to-Source Voltage (Continuous) 100
V
Drain-to-Source Voltage (up to 10,000 5ms pulses at 150˚C) 120
I
D
Continuous 10
A
Pulsed (25°C, T
PULSE
= 300 µs) 42
V
GS
Gate-to-Source Voltage 6
V
Gate-to-Source Voltage -4
T
J
Operating Temperature -55 to 150
°C
T
STG
Storage Temperature -55 to 150
# Dened by design. Not subject to production test.
Rad Hard eGaN® transistors have been specically designed for critical applications in the high
reliability or commercial satellite space environments. GaN transistors oer superior reliability
performance in a space environment because there are no minority carriers for a single event,
and as a wide band semiconductor there is less displacement for protons and neutrons, and
additionally, there is no oxide to breakdown. These devices have exceptionally high electron
mobility and a low-temperature coecient resulting in very low R
DS(on)
values. The lateral
structure of the die provides for a very low gate charge (Q
G
) and extremely fast switching times.
These features enable faster power supply switching frequencies resulting in higher power
densities, higher eciencies, and more compact designs.
Thermal Characteristics
PARAMETER TYP UNIT
R
θJC
Thermal Resistance, Junction-to-Case (Case TOP)
2.8
°C/W
R
θJB
Thermal Resistance, Junction-to-Board (Case BOTTOM)
5.6
R
θJA_JEDEC
Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB)
130
R
θJA_EVB
Thermal Resistance, Junction-to-Ambient (EPC9006C EVB)
88
Static Characteristics (T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BV
DSS
Drain-to-Source Voltage V
GS
= 0 V, I
D
= 100 μA 100 V
I
DSS
Drain-Source Leakage V
DS
= 100 V, V
GS
= 0 V 0.5 100 μA
I
GSS
Gate-to-Source Forward Leakage V
GS
= 5 V 0.001 0.6
mA
Gate-to-Source Forward Leakage
#
V
GS
= 5 V, T
J
= 125°C 0.1 1.3
Gate-to-Source Reverse Leakage V
GS
= -4 V 0.5 100 μA
V
GS(TH)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= 1.4 mA 0.8 1.4 2.5 V
R
DS(on)
Drain-Source On Resistance V
GS
= 5 V, I
D
= 6 A 18 30 mΩ
V
SD
Source-to-Drain Forward Voltage
#
I
S
= 0.5 A, V
GS
= 0 V 1.7 V
Preliminary
eGaN® FET DATASHEET
EPC7003
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2
0 0.5 1.0 1.5 2.0 2.5 3.0
I
D
– Drain Current (A)
Figure 1: Typical Output Characteristics at 25 °C
V
DS
– Drain-to-Source Voltage (V)
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
40
35
30
25
20
15
10
5
0
R
DS(on)
– Drain-to-Source Resistance (mΩ)
V
GS
– Gate-to-Source Voltage (V)
80
100
60
40
20
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 3: R
DS(on)
vs. V
GS
for Various Drain Currents
I
D
= 3 A
I
D
= 6 A
I
D
= 9 A
I
D
= 12 A
I
D
– Drain Current (A)
V
GS
– Gate-to-Source Voltage (V)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Typical Transfer Characteristics
25˚C
125˚C
V
DS
= 3 V
40
35
30
25
20
15
10
5
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
25˚C
125˚C
I
D
= 6 A
R
DS(on)
– Drain-to-Source Resistance (mΩ)
V
GS
– Gate-to-Source Voltage (V)
70
60
50
40
30
20
10
0
Dynamic Characteristics
#
(T
J
= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
ISS
Input Capacitance
V
DS
= 50 V, V
GS
= 0 V
230 313
pF
C
RSS
Reverse Transfer Capacitance 0.6
C
OSS
Output Capacitance 119 143
C
OSS(ER)
Eective Output Capacitance, Energy Related (Note 1)
V
DS
= 0 to 50 V, V
GS
= 0 V
144
C
OSS(TR)
Eective Output Capacitance, Time Related (Note 2) 188
R
G
Gate Resistance 1.3 Ω
Q
G
Total Gate Charge V
DS
= 50 V, V
GS
= 5 V, I
D
= 6 A 1.8 2.5
nC
Q
GS
Gate-to-Source Charge
V
DS
= 50 V, I
D
= 6 A
0.6
Q
GD
Gate-to-Drain Charge 0.3
Q
G(TH)
Gate Charge at Threshold 0.4
Q
OSS
Output Charge V
DS
= 50 V, V
GS
= 0 V 9.4 11
Q
RR
Source-Drain Recovery Charge 0
All measurements were done with substrate connected to source.
# Dened by design. Not subject to production test.
Note 1: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 2: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.