RX660 Group

Renesas MCUs

Datasheet

R01DS0393EJ 01 0 0 Rev.1.00 Page 1 of 123

Mar 18, 2022

Features

■ 32-bit RXv3 CPU core



Maximum operating frequency: 120 MH z

Capable of 709 CoreMark in operation at 120 MHz



A collective register bank save function is available.



Supports the mem ory protection unit (MPU)



JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture



Operation from a sing le 2.7- to 5.5-V supply



Deep software standby mode with the RTC continuing to run



Four low-power mode s

■ On-chip code flash memory



Supports versions with up to 1 Mbyte of ROM



No waiting for access in 12 0-MHz operation



User code is programmable by on-board or off-board programming.



Programming/erasing a s background operations (BG Os)

■ On-chip data flash memory



32 Kbytes, reprogrammable up to 100,000 times



Programming/erasing a s background operations (BG Os)

■ On-chip SRAM



128 Kbytes of SRAM (no wait states)

■ External address space



Buses for full-speed data transfer (maximum operating frequency of

40 MHz)



Four CS areas



8- or 16-bit bus space is selectable per area

■ Data transfer



DMACAa: 8 channels



DTCb: 1 ch ann el

■ ELC



Module operation ca n be initiated by event signals without u sing

interrupts



Linked operation betwee n modules is possible when the CPU is in

sleep mode

■ Reset and supply management



Power-on reset (POR)



Low voltage d etectio n (LVD )

■ Clock functions



The main clock oscillato r is connectab le to an 8- to 2 4 -MHz ex ternal

crystal resonator and usable as the PLL reference clock.



A sub-clock oscillator connectable to a 32.768-kHz cry stal resonator



Internal 240-kHz LOC O and HOCO selectable from 16, 18, and 20

MHz



120-kHz clock for the IWDTa

■ Real-time clock



Adjustment functions (30 seconds, leap year, and error)



Real-time clock counting and binary counting modes are selectable



Time capture in response to an event-signal input

■ Independent watchdog timer



120-kHz IWD T -dedicated on-chip oscillator clock operation

■ Useful functions for IEC60730 compliance



Oscillation-stoppage detection, func tions for self-diagnosis and

detection of disconnection for the A/D converter, clock frequency

accuracy measurement circuit, independent watchdog timer, RA M

test-assisting function by DOC, and CRCA, etc.



against overwriting

■ Remote control signal receiver

■ Various communications interfaces



CAN FD : Compliant with ISO 11898-1:2015, standard frame and

extended frame (1 channel)



SCIk, SCIm, and SCIh with multiple functionalities (up to 13

channels)

Choose from among asynchronous mo de, clock -synchro nou s mod e,

smart-card interface mode, simplified SPI, simplified I

C, and

extended serial mode.



SCIm with 16-byte transmission and reception FIFOs (up to 2

channels)



The I

C bus interfaces (RIICa) for transfer at up to 400 kbps (fast

mode), capable of SMBus operation (2 channels)



RSPId (1 channel) for transfer at up to 30 Mbps

■ Up to 19 extended-function timers



16-bit MTU3a



8-bit TMRb (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2

channels)

■ 12-bit A/D converter



Single 12-bit unit (24 channels)



Self diagnosis, detection of analog input disconnection

■ Analog Comparator (CMPC): 4 channels

■ 12-bit D/A converter (R12DAb): 2 channels



Usable as a referenc e voltage for the analog co mparator

■ Temperature sensor for measuring temperature

within the chip

■ Up to 134 pins for general I/O ports



5-V tolerance, open drain, input pull-up, switchable driving ab ility

■ Operating temp. range



D-version: –40



C to +85





G-version: –40



C to +105



PLQP0144KA-B 20 × 20 mm, 0.5 mm pitch

PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch

PLQP0080KB-B 12 × 12 mm, 0.5 mm pitch

PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch

PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch

120-MHz 32-bit RX MCU, on-chip FPU, 709 CoreMark, Supportive of 5V power supply, up to 1-MB flash memory,

up to 128-KB SRAM, 32-KB data flash memory, various communications interfaces, including CAN FD,

12-bit A/D converter, 12-bit D/A converter, Analog comparator, RTC, Remote control signal receiver

R01DS0393EJ0100

Rev.1.00

Mar 18, 2022

Features

RX660 Group 1. Overview

R01DS0393EJ 01 0 0 Rev.1.00 Page 2 of 123

Mar 18, 2022

1. Overview

1.1 Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different

packages.

Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the

modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions

for Different Packages.

Table 1.1 Outline of Specifications (1/8)

Classification Module/Function Description

CPU CPU  Maximum operating frequency: 120 MHz

 32-bit RX CPU (RXv3)

 Minimum instruction execution time: One instruction per state (cycle of the system

clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 113 instructions

Instructions installed as standard: 111

Basic instructions: 77

Single-precision floating-point operation instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32 / 32 → 32 bits

 Barrel shifter: 32 bits

FPU  Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

function

 Fast collective saving and restoration of the values of CPU registers

 16 save register banks

Memory Code flash memory  Capacity: 1 Mbyte/512 Kbytes

 120 MHz, no-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

 Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

Data flash memory  Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID  12-byte unique ID for the device

RAM  Capacity: 128 Kbytes

 120 MHz, no-wait access

Operating modes  Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (for the SCI interface)

Boot mode (for the FINE interface)

User boot mode

 Selection of operating mode by register setting

Single-chip mode

User boot mode

On-chip ROM disabled extended mode

On-chip ROM enabled extended mode

 Endian selectable