FN6660 Rev.9.02 Page 1 of 16
Jun 11, 2020
FN6660
Rev.9.02
Jun 11, 2020
ISL80102, ISL80103
High Performance 2A and 3A Linear Regulators
DATASHEET
The ISL80102 and ISL80103 are low voltage, high-current,
single output LDOs specified for 2A and 3A output current,
respectively. These LDOs operate from the input voltages of
2.2V to 6V and are capable of providing the output voltages of
0.8V to 5.5V.
An external capacitor on the soft-start pin provides adjustment
for applications that demand inrush current less than the
current limit. The ENABLE feature allows the part to be placed
into a low quiescent current shutdown mode. A submicron
BiCMOS process is used for this product family to deliver
best-in-class analog performance and overall value.
These CMOS (LDOs) consume significantly lower quiescent
current as a function of load over bipolar LDOs, so they are
more efficient and allow packages with smaller footprints. The
quiescent current has been modestly compromised to enable
a leading class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
Related Literature
For a full list of related documents, visit our website
• ISL80102
, ISL80103 product pages
Features
• Stable with ceramic capacitors (Note 11)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
• ±1.8% V
OUT
accuracy assured over line, load, and T
J
= -40°C
to +125°C
• Very low 120mV dropout voltage at 3A (ISL80103)
• Very fast transient response
•Excellent 62dB PSRR
• 49µV
RMS
output noise
• Power-good output
• Adjustable inrush current limiting
• Short-circuit and over-temperature protection
• Available in a 10 Ld DFN
Applications
•Servers
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
•Routers and switchers
FIGURE 1. TYPICAL APPLICATION DIAGRAM FOR ADJUSTABLE OUTPUT VOLTAGE VERSION
ISL80102, ISL80103
V
IN
9
V
IN
10
ENABLE
7
SS
6
GND
2.5V ±10%
C
IN
10µF
V
IN
*C
SS
5
PG
4
V
OUT
1
V
OUT
2
V
OUT
1.8V
C
OUT
10µF
R
PG
100kΩ
ADJ
3
PGOOD
R
1
10kΩ
R
4
1.0kΩ
**C
PB
47pF
EN
OPEN DRAIN COMPATIBLE
*CSS is optional (see Note 12 on page 5).
**C
PB
is optional (see “Functional Description” on page 12 for more information).
R
3
2.61kΩ
ISL80102, ISL80103
FN6660 Rev.9.02 Page 2 of 16
Jun 11, 2020
Pin Configuration
10 LD 3x3 DFN
TOP VIEW
Block Diagram
TABLE 1. COMPONENTS VALUE SELECTION
V
OUT
(V)
R
TOP
(kΩ)
R
BOTTOM
(Ω)
C
PB
(pF)
C
OUT
(µF)
5.0 2.61 287 47 10
3.3 2.61 464 47 10
2.5 2.61 649 47 10
1.8
(Note 1) 2.61 1.0k 47 10
1.8
(Note 1) 2.61 1.0k 82 22
1.5 2.61 1.3k 82 22
1.2 2.61 1.87k 150 47
1.0 2.61 2.61k 150 47
0.8 2.61 4.32k 150 47
NOTE:
1. Either option can be used depending on cost/performance
requirements
2
3
4
1
5
9
8
7
10
6
V
OUT
V
OUT
ADJ
PG
GND
V
IN
V
IN
DNC
ENABLE
SS
EPAD
Pin Descriptions
PIN
NUMBER
PIN
NAME DESCRIPTION
1, 2 V
OUT
Output voltage pin
3 ADJ ADJ pin for externally set V
OUT
.
4PGV
OUT
in regulation signal. Logic low defines when
V
OUT
is not in regulation. Must be grounded if not
used.
5GNDGND pin
6 SS External cap adjusts inrush current. Leave this pin
open if not used.
7ENABLE V
IN
independent chip enable. TTL and CMOS
compatible.
8 DNC Do not connect this pin to ground or supply. Leave
floating.
9, 10 V
IN
Input supply pin
EPAD EPAD must be connected to a copper plane with as
many vias as possible for proper electrical and
optimal thermal performance.
10µA 10µA
R
7
R
8
R
9
R
5
M5
M4
EN
EN
EN
ENEN
ENABLE
M7
500mV
485mV
500mV
M3
POWER PMOS
M1
V
IN
V
OUT
R
1
R
4
*R
3
GND
PG
ADJ
M2
+
-
+
-
+
-
+
-
+
-
+
-
+
-
V TO I
SS
IL/10000
IL
M6
M8 EN
*R
3
is open for ADJ versions.
FIGURE 2. BLOCK DIAGRAM