Technical Document

DDR Termination Regulator TPL51200 Application Notes

This document contains intellectual property and trade secrets of 3PEAK INCORPORATED.

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No unauthorized copy or distribution without written consent from 3PEAK INCORPORATED.

DC20230304A0

DDR Termination Regulator TPL 51200

Application Notes

In the memory application circuit, for data

transmission with fewer Bit lines, the

traditional passive bus termination resistor

(Thevenin termination) is used to match the

DDR transmission line impedance with the

power supply impedance, which can

effectively reduce the cost (as shown in Figure

1).

Figure 1. Source Bus Terminal Wiring Diagram

When Q1 is turned on, Q2 is turned off, and

the current flows from VDDQ to VTT through

resistors RS and RT. At this time, the VTT

terminal sinks current, the receiver input

voltage (Vin) is higher than Vref, and the

receiver realizes the digital signal "1" input;

When Q2 is turned on, Q1 is turned off, the

current flows from VTT to ground through RT

and RS through Q2. At this time, the VTT

terminal sources current, and Vin is lower than

Vref, and the receiver realizes the digital signal

"0" input.

To obtain faster data transmission rate and

ensure stable data transmission, more and

more industrial, automotive, communication,

and portable electronic systems use DDR

memory for data transmission.

In DDR memory, multiple Bit lines share a VTT

voltage. To ensure the accuracy of DDR data

read and write at the receiving end, Vin must

be greater than or less than the voltage Vref of

125 mV to ensure the correct flipping of the

comparator.

Taking DDR4 as an example, suppose there

are 50 Bit lines in total. At this time, the

traditional passive terminal resistor must

consider the power consumption issue,

especially when the high-bit line and the low-

bit line are asymmetrical, and the RP

resistance has to be reduced.

Generally, the on-state impedance of Q1 and

Q2 is dozens of ohms (take 20 Ω as an

example). In DDR4, when the high bits are

more than the low bits, VTT absorbs the

current. To ensure the accuracy of data read

Technical Document

DDR Termination Regulator TPL51200 Application Notes

This document contains intellectual property and trade secrets of 3PEAK INCORPORATED.

2 / 3

No unauthorized copy or distribution without written consent from 3PEAK INCORPORATED.

DC20230304A0

and write, the calculation formula is:

(VDDQ

− VTT) ×

[

RQ1 + RS + RT

]

+ VTT = (1.2

− 0.6) ×

+ 0.6 ≥ 0.725

It can be calculated that the VTT

voltage cannot be less than 0.428 V.

Taking DDR4 as an example, when all the

bits are low, to ensure the VTT voltage, the

RP resistance cannot exceed 1Ω, which will

bring a power consumption of 0.92 W. The

calculation formula is:

VDDQ2

RP + RP//

RT + RS + RQ2

1.22

1 +

The RP resistance brings an additional 0.78 W

of power consumption, which is unacceptable.

Compared with passive termination, the

advantage of active termination (as shown in

Figure 2) is that it can provide a stable VTT

voltage with high current output capability.

This can avoid data read and write

errors caused by impedance matching issues

at the source, and greatly improve system

efficiency by eliminating the Rp voltage divider.

T PL 51200 Functional Block Diagram

Figure 2

As shown in Figure 1 and Figure 2, VTT is an

active terminal with both sink and source

capabilities. Its working mode is the same as

that of passive termination, but in the case of

sink or source current, the active termination

automatically adjusts the VTT voltage through

an internal loop to ensure that the VTT voltage

is always equal to 1/2*VDDQ.

The TPL51200 designed by 3PEAK is a

high-performance linear regulator suitable

for DDR memory bus terminal power

supply.

Compared with other DCDC solutions, the

TPL51200 reduces the number of

components, saving board space and system