Application Note

R01AN6628EU0100 Rev.1.00 Page 1 of 19

Oct.06.22

Renesas RA Family

RA Ethernet D e sign and Cust om PHY Setu p using FSP

Introduction

This application note describes Ethernet designs in gener al, provides a brief introduction to the RA Ethernet

controller and interface to the PHY peripheral. It provides the design guidelines, when using the RA MCU

with RMII modes for Ethernet specific applications.

The app note also covers the usage of FSP configurator to add the Ethernet module and configure it

correctly. Additionally, it covers the adding new PHY to custom boards and software support using FSP.

App note also covers the usage of Wake-on-LAN (WOL) feature and using the LPM mode in Ethernet based

designs. Finally, debugging of an Ethernet design based on RA is covered.

Applies to:

• RA MCU Group wi th Ether net Per ipher a ls

Contents

1. Introduction to Ethernet Connectivity ....................................................................................... 2

1.1 General Overview .................................................................................................................................... 2

1.2 Ethernet MAC Controller ......................................................................................................................... 2

1.3 Ethernet DMA Controller ......................................................................................................................... 4

1.4 Ethernet PH Y ........................................................................................................................................... 5

2. General Design Guidelines ...................................................................................................... 6

2.1 Design Guidelines while using Arm TrustZone MCU .............................................................................. 6

2.2 Sample Design while using RA MCU with RMII ...................................................................................... 7

3. FSP Configuration for Ethernet Module ................................................................................... 7

3.1 Ethernet Driver configuration ................................................................................................................... 7

3.2 PHY Configuration ................................................................................................................................... 9

3.3 Adding a New PHY Device .................................................................................................................... 10

3.4 Signal Drive Strength Configuration ...................................................................................................... 12

4. Support of Low Power Modes and Wake-on-LAN .................................................................. 13

5. Debugging ............................................................................................................................. 14

5.1 Debugging RA Ethernet Controller using FSP ...................................................................................... 14

5.2 Debugging Ethernet PHY using FSP .................................................................................................... 15

5.3 Debugging R A Ether net Designs .......................................................................................................... 16

6. FAQs ..................................................................................................................................... 17

6.1 RA Ethernet FAQs ................................................................................................................................. 17

6.2 Renesas Rulz ........................................................................................................................................ 17

7. References ............................................................................................................................ 17

Renesas RA Family RA Ethernet Design and Custom PHY Setup using FSP

R01AN6628EU0100 Rev.1.00 Page 2 of 19

Oct.06.22

8. Known Issues ........................................................................................................................ 17

Revision His tory ............................................................................................................................ 19

1. Introduction to Etherne t Conne ctivity

Ethernet connectivity is one of the commonly used technologies in the data communications space, typically

using a Local Area Network (LAN). Ethernet is based on the IEEE 802.3 standards supporting different

speeds and mediums on which it runs. In recent years, Ethernet communication is used in home automation,

industrial automation, and consumer electronics products. Ethern et is also used e x tens ively in IoT

applications as the default connectivity option. In Power over Ethernet (POE) based systems, power for the

system can be derived from the communication line, without additional power connections for the system,

which enables Ethernet as a perfect choice of connectivity for variety of applications as well.

1.1 General Overview

For networking connectivity challenges, Renesas Microcontrollers (MCUs) and Microprocessors (MPUs) with

Ethernet s u pport mak e it easy to implement Ethernet solution in your applications.

The Renesas RA group of microcontrollers (MCUs) uses the high-performance Arm

Cortex

core and offers

Ethernet MAC with built in DMA, to ensure high data throughput.

Renesas RA Ethernet provides the following functionality:

• 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet

• Half- and full-duplex support

• Transmit/receive processing (Blocking and Non-Blocking)

• Auto-negotiation support

• Magic packet (Magic Pattern) detection mode support

• Flow control compliant with IEEE802.3x

• Media Independent Interface (MII), Reduced Media Independent Interface (RMII), compliant with the

• IEEE802.3u standard

• MDC/MDIO Management Interface for PHY Register Configuration

• Wake-on-LAN (WOL) signal output

• Hardware filtering of received multicast packets with a MAC address.

Figure 1. Ethernet Architecture Block Diagram

1.2 Ethern et MAC Controller

RA MCUs provide a one or two channel Ethernet Controller (ETHERC) compliant with the Ethernet or

IEEE802.3 Media Access Control (MAC) layer protocol. Each ETHERC channel has one channel of the MAC

layer interface. Connecting the MCU to the physical layer LSI (PHY-LSI) allows transmission and reception

of frames compliant with the Ethernet/IEEE802.3 standard. The ETHERC is connected to the Ethernet DMA

Controller (EDMAC), so data can be transferred without much interv enti on of the CPU. Figure 2 shows the

RA Ethernet Module blocks.