Crystal oscillator
Specifications (characteristics)
Item
Symbol
Specifications
Conditions / Remarks
Output frequency range
fo
25 MHz to 500 MHz
Please contact us for available frequencies.
Supply voltage
V
CC
D: 2.5 V ± 5 %, C: 3.3 V ± 5 %
Storage temperature
T_stg
-55 C to +125 C
Operating temperature
T_use
G: -40 C to +85 C, H: -40 C to +105 C
Frequency tolerance
f_tol
D: ±25 × 10
-6
Max.
J: ±50 × 10
-6
Max.
Includes initial frequency tolerance, frequency /
temperature characteristics, frequency / voltage
coefficient and 10 years aging (+25 °C)
Current consumption
I
CC
35 mA Max.
25 MHz ≤ fo < 212 MHz
OE or S T = V
CC
,
L_HCSL = 50 Ω
40 mA Max.
212 MHz ≤ fo < 500 MHz
Disable current
I_dis
25 mA Max.
OE = GND
Stand-by current
I_std
30 μA Max.
S T = GND, T_use Max. = +85 °C
60 μA Max.
S T = GND, T_use Max. = +105 °C
Symmetry
SYM
45 % to 55 %
At output crossing point
Output voltage
V
OH
0.5 V to 0.7 V
25 MHz ≤ fo < 212 MHz
Output option: A
0.4 V to 0.65 V
212 MHz ≤ fo < 500 MHz
0.6 V to 0.8 V
25 MHz ≤ fo < 212 MHz
Output option: B
0.5 V to 0.75 V
212 MHz ≤ fo < 500 MHz
V
OL
-0.15 V to +0.15 V
Differential swing
V
SW
0.7 V to 1.4 V
Output option: A
0.8 V to 1.6 V
Output option: B
Crossing voltage
V
CR
0.25 V to 0.55 V
Rise time / Fall time
tr/tf
0.7 ns Max.
20 % - 80 % (V
OH
- V
OL
)
Differential output
rise slew rate / fall slew rate
Rr/Rf
2 V/ns to 10 V/ns
Between -0.15 V and 0.15 V of differential output
Output load condition
L_HCSL
50 Ω
Input voltage
V
IH
70 % V
CC
Min.
OE or S T terminal
V
IL
30 % V
CC
Max.
Output enable time
tsta_oe
500 ns Max.
t = 0 at OE = 70 % V
CC
tsta_st
10 ms Max.
t = 0 at S T = 70 % V
CC
Output disable time
tstp_oe
100 ns Max.
t = 0 at OE = 30 % V
CC
tstp_st
100 ns Max.
t = 0 at S T = 30 % V
CC
Start-up time
t_str
10 ms Max.
t = 0 at 90 % V
CC
Phase jitter
t
PJ
200 fs Max.
25 MHz ≤ fo < 100 MHz
Offset frequency
fo < 50 MHz:
12 kHz to 5 MHz
fo ≥ 50 MHz:
12 kHz to 20 MHz
90 fs Max.
100 MHz ≤ fo ≤ 156 MHz
70 fs Max.
156 MHz < fo ≤ 212 MHz
60 fs Max.
212 MHz < fo ≤ 391 MHz
50 fs Max.
391 MHz < fo ≤ 500 MHz
Jitter
t
c-c
60 ps Max.
Cycle to cycle jitter (Peak to Peak)
PCIe jitter limits
for CC architecture
-
0.1 ps Max.
For PCIe Gen5
0.06 ps Max.
For PCIe Gen6
Product name
Product Name
(Standard form)
a: Model b: Output (H: HCSL) c: Frequency d: Supply voltage e: Frequency tolerance
f: Operating temperature g: Function h: Output disable type (Z: High impedance) i: Output option
External dimensions
(Unit:mm)
Footprint (Recommended)
(Unit:mm)
SG2520HGN SG2016HGN
Pin map
Pin
Connection
1
OE or S T
2
N.C. (Open or V
CC
)
3
GND
4
OUT
5
OUT
6
V
CC
SG2520HGN
SG2016HGN
A
0.88
0.85
B
0.76
0.574
C
1.38
1.15
D
1.99
1.564
E
0.63
0.574
SG2016 HGN
100.000000MHz
C
D
H
P
Z
A
a b
c
d
e
f
g
h
i
d: Supply voltage
e: Freq. tolerance
f: Operating temp.
g: Function
i: Output option
C
3.3 V Typ.
D
±25 × 10
-6
G
-40 C to +85 C
P
OE
A
V
SW
= 0.7 V to 1.4 V
D
2.5 V Typ.
J
±50 × 10
-6
H
-40 C to +105 C
S
S T
B
V
SW
= 0.8 V to 1.6 V
CRYSTAL OSCILLATOR (SPXO)
OUTPUT : HCSL
SG2016 / 2520HGN
•Frequency range : 25 MHz to 500 MHz
•Supply voltage : 2.5 V Typ. / 3.3 V Typ.
•Frequency tolerance : ±25 × 10
-6
, ±50 × 10
-6
•Operating temperature : -40 C to +85 C, -40 C to +105 C
•Function : Output enable (OE) or Standby (S T )
•Phase jitter : 90 fs Max. (100 MHz < fo ≤ 156 MHz, V
CC
= 2.5 V, 3.3 V)
•PCIe Gen5,6 Jitter specification compliant
Product Number
SG2016HGN: X1G006221xxxx15
SG2520HGN: X1G005891xxxx15
In order to achieve optimum jitter performance, it is recommended that
0.1 μF and 10 μF bypass capacitors should be connected between V
CC
and GND and placed as close to the V
CC
pin as possible.
Note:
OE or S T pin = HIGH or “Open”:
Specified frequency output.
OE or S T pin = LOW:
Output is high impedance
B
E
D
A
C
SG2520HGN
(2.5 × 2.0 × 0.74 mm)
SG2016HGN
(2.0 × 1.6 × 0.63 mm)
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