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e2v semiconductors SAS 2011
Quad ADC EV8AQ160
Application Note
1. Introduction
The aim of this application is to provide you with some recommendations to implement the
EV8AQ160 Quad 8-bit 1.25 Gsps ADC in your system.
It first presents the ADC input/output interfaces and then provides some recommendations in
regards to the device settings and board layout in order to obtain the best performance of the device.
This document applies to the EV8AQ160 8-bit 1.25 Gsps ADC.
2. EV8AQ160 ADC Input Terminations
2.1 Clock Input
It is recommended to drive the Quad ADC input clock in a differential mode in order to optimize the
performance of the ADC and minimize the injection of noise in the die ground plane.
As the clock input common mode is 1.8V, it is recommended to AC couple the clock signal, as illus-
trated in Figure 2-1.
Figure 2-1. EV8AQ160 ADC Clock Input Termination Scheme
10 nF
10 nF
Differential
sinewave
50Ω
Source
CLK
CLKN
ADC Clock Input Buffer
V
ICM
= ~1.8V
50Ω
50Ω
GND
5.25 pF
GND
11.06 KΩ
12.68 KΩ
V
CC
= 3.3V
0824D–BDC–04/11