91
Process C3017
CMOS 3µm
10 Volt Analog Mixed Mode
N-Channel T ransistor Symbol Minimum Typical Maximum Unit Comments
Threshold Voltage VT
N
0.6 0.8 1.0 V 100x4µm
Body Factor
γ
N
0.6 V
1/2
100x4µm
Conduction Factor β
N
42 47 52
µ
A/V
2
100x100
µ
m
Effective Channel Length Leff
N
2.85 3.2 3.55
µ
m 100x4
µ
m
Width Encroachment
∆
W
N
0.7
µm Per side
Punch Through V oltage
BVDSS
N
12 V
Poly Field Threshold Voltage
VTF
P(N)
12 V
P-Channel T ransistor Symbol Minimum Typical Maximum Unit Comments
Threshold Voltage VT
P
–0.6 –0.8 –1.0 V 100x4µ
m
Body Factor
γ
P
0.55 V
1/2
100x4µm
Conduction Factor β
P
13 15 19 µA/V
2
100x100µm
Effective Channel Length Leff
P
2.85 3.2 3.55 µ
m 100x4µ
m
Width Encroachment ∆
W
P
0.9 µ
m Per side
Punch Through V oltage
BVDSS
P
–12 V
Poly Field Threshold Voltage
VTF
P(P)
–12 V
Diffusion & Thin Films Symbol Minimum Typical Maximum Unit Comments
Well (field) Sheet Resistance
ρ
P-well(f)
3.2 4.8 6.5 KΩ/o P-well
N+ Sheet Resistance
ρ
N+
16 21 27 Ω
/
o
N+ Junction Depth x
jN+
0.8 µm
P+ Sheet Resistance
ρ
P+
50 80 100 Ω/o
P+ Junction Depth x
jP+
0.7
µ
m
Gate Oxide Thickness T
GOX
44 48 52 nm
Interpoly Oxide Thickness T
P1P2
60 nm
Gate Poly Sheet Resistance
ρ
POLY1
15 22 30
Ω/
o
Bottom Poly Sheet Res.
ρ
POLY2
15 22 30 Ω
/
o
Metal-1 Sheet Resistance
ρ
M1
50 mΩ/o
Metal-2 Sheet Resistance
ρ
M2
30 m
Ω
/o
Passivation Thickness T
PASS
200+900 nm oxide+nit.
Capacitance Symbol Minimum Typical Maximum Unit Comments
Gate Oxide C
OX
0.66 0.72 0.78 fF/µm
2
Metal-1 to Poly-1 C
M1P
0.0523 fF/µm
2
Metal-1 to Silicon C
M1S
0.26 0.30 0.34 fF/µm
2
Metal-2 to Metal-1 C
MM
0.033 0.0384 0.041 fF/µm
2
Poly-1 to Poly-2 C
P1P2
0.51 0.57 0.63 fF/µm
2
Electrical Characteristics
T=25
o
C Unless otherwise noted
ISO 9001 Registered
®
© Daily Silver IMP
92
C3017
Process C3017
Starting Material P <100> N+/P+ Width/Space 3.0 / 3.0µm
Starting Mat. Resistivity 15 - 25 Ω-cm N+ To P+ Space 12
µm
Typ. Operating Voltage 10V Contact To Poly Space 2.5
µ
m
Well Type P-well Contact Overlap Of Diffusion 1.5
µ
m
Metal Layers 2 Contact Overlap Of Poly 1.0
µm
Poly Layers 2 Metal-1 Overlap Of Contact 1.0µm
Contact Size 2.0x2.0
µm Metal-1 Overlap Of Via 1.75µ
m
Via Size 2.0x2.0µm Metal-2 Overlap Of Via 1.5
µm
Metal-1 Width/Space 3.5 / 2.5µm Minimum Pad Opening 100x100µm
Metal-2 Width/Space 5.0 / 3.0
µm Minimum Pad-to-Pad Spacing 5.0µ
m
Gate Poly Width/Space 4.0 / 2.5µm Minimum Pad Pitch 80.0 µm
Special Feature of C3017 Process: P-well analog process with double metal CMOS 3.0 µm
technology.
Physical Characteristics
5
4
3
2
1
0
012345678910
ID vsVD, W/L = 20/4.0
Drain Voltage (v) V
DS
n-ch Transistor IV characteristics of a 20/4.0 device
Drain Current (mA) I
DS
V
GS
= 10V
V
GS
= 9.0V
V
GS
= 8.0V
V
GS
= 7.0V
V
GS
= 6.0V
V
GS
= 5.0V
V
GS
= 4.0V
V
GS
= 3.0V
V
GS
= 2.0V
-3
-2.5
-2
-1.5
-1
-.5
0
012345678910
ID vsVD, W/L = 20/4.0
Drain Voltage (v) V
DS
p-ch Transistor IV characteristics of a 20/4.0 device
Drain Current (mA) I
DS
V
GS
= -10V
V
GS
= -9.0V
V
GS
= -8.0V
V
GS
= -7.0V
V
GS
= -6.0V
V
GS
= -5.0V
V
GS
= -4.0V
V
GS
= -3.0V
V
GS
= -2.0V
Cross-sectional view of the C3017 process
Second metal
SIO
2
LTO
p
+
p
+
p
+
n
+
p
Field Oxide
p-well contact
Drain
Poly gate
p-well
source
Drain
Source
N
–
substrate contact
Bottom poly
Contact
Poly gate
VIA
Metal 1
N
+
substrate
n
+
n
+
A1
p p
SIO
2
n-epi
Sidewall spacer