Key Features
◆
Ultra-Fast response for Fast-20 SCSI applications
◆
35MHz channel bandwidth
◆
3.3V operation
◆
Less than 3pF output capacitance
◆
375µA Sleep-mode current
◆
Thermally self limiting
◆
No external compensation capacitors
◆
Implements 8-bit or 16-bit (wide) applications
◆
Compatible with active negation drivers
(60mA/channel)
◆
Compatible with passive and Active terminations
◆
Approved for use with SCSI 1, 2, 3 and UltraSCSI
◆
Hot swap compatible
◆
Pin-for-pin compatible with DS21S07A/2105
Block Diagrams
–
+
Current
Biasing
Circuit
Thermal
Limiting
Circuit
24mA Current
Limiting Circuit
Term Power
DATA OUTPUT
PIN DB (0)
1 of 9 Channels
DISABLE PIN
1.4V
2.85V
5115_01.eps
9-Line SCSI T
9-Line SCSI T
er
er
minat
minat
or
or
– 35MHz Channel Bandwidt
– 35MHz Channel Bandwidt
h
h
The IMP5115 SCSI terminator is part of IMP's family of high-perfor-
mance, adaptive, non-linear mode SCSI products, which are designed to
deliver true UltraSCSI performance in SCSI applications. The low voltage
BiCMOS architectur e employed in its design offers performance superior
to older linear passive and active techniques. IMP's SCSI termination
architecture employs high-speed adaptive elements for each channel,
thereby providing the fastest response possible — typically 35MHz,
which is 100 times faster than the older linear regulator/terminator
approach used by other manufacturers. Products using this older linear
regulator appr oach have bandwidths which ar e dominated by the output
capacitor and which are limited to 500KHz (see further discussion in the
Functional Description section). This new architectur e also eliminates the
output compensation capacitor required in earlier terminator designs.
Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond —
providing the highest performance alternative available today.
Another key improvement offered by the IMP5115 lies in its ability to
insure reliable, error-free communications even in systems which do not
adhere to recommended SCSI hardware design guidelines, such as the
use of improper cable lengths and impedances. Fr equently, this situation
is not controlled by the peripheral or host designer and, when problems
occur, they are the first to be made aware of the problem. The IMP5115
architecture is much more tolerant of marginal system integrations.
Recognizing the needs of portable and configurable peripherals, the
IMP5115 has a TTL compatible sleep/disable mode. Quiescent current
is typically 375µA in this mode, while the output capacitance is also
less than 3pF. The obvious advantage of extended battery life for
portable systems is inherent in the product's sleep-mode feature.
Additionally, the disable function permits factory-floor or production-
line configurability, reducing inventory and product-line
diversity costs. Field configurability can also be accom-
plished without physically removing components which,
often times results in field returns due to mishandling.
Reduced component count is also inherent in the IMP5115
architecture. Traditional termination techniques require
large stabilization and transient protection capacitors of up
to 20µF in value and size. The IMP5115 architecture does
not require these components, allowing all the cost savings
associated with inventory, board space, assembly, reliability,
and component costs.
1
IMP5
IMP
5
1
1
1
1
5
5
Data Communications 1
D
AT
AC
OMMUNI
C
A
TIONS
Daily Silver IMP
2
Pin Configuration
Ordering Information
Absolute Maximum Ratings
1
8
GND
1TERM POWER
D Package
9NC
7
NC 10 NC
6D4 11 D5
5D3 12 D6
4D2 13 D7
3
D1 14 D8
2D0 15 NC
16 DISABLE
5115__02.eps
IMP5115
8
GND
1
TERM POWER
DW Package
9NC
7
NC 10 D5
6D4 11 D6
5D3 12 D7
4D2 13 D8
3
D1 14 NC
2
D0 15 NC
16 DISABLE
5115__02a.eps
IMP5115
SO-16 SOWB-16
1
TERM POWER
PWP Package
7D4 14 D6
8HEAT SINK/GND 13 D5
9
NC 12 HEAT SINK/GND
10GND 11 NC
6
D3 15 D7
5
D2 16 D8
4
D1 17 NC
3D0 18 HEAT SINK/GND
2
HEAT SINK/GND 19 NC
20 DISABLE
5115_02b.eps
IMP5115
TSSOP-20
rebmuNtraPegnaRerutarepmeTegakcaP
DC5115PM
I0
°
521otC
°
CO
ScitsalPnip-61
TDC5115PMI0° 521otC °COScitsalPnip-61,leeRdnaepaT
WDC5115PMI0° 521otC °CBWOScitsalPnip-61
TWDC5115PM
I0
°
521otC
°
CB
WOScitsalPnip-61,leeRdnaepaT
PWPC5115PMI0° 521otC °CPOSSTcitsalPnip-02
TPWPC5115PMI0° 521otC °CPOSSTcitsalPnip-02,leeRdnaepaT
3ta.10t_5115
Thermal Data
Continuous Termination Voltage . . . . . . . . . . . 10V
Continuous Output Voltage Range . . . . . . . . 0V to 5.5V
Continuous Disable Voltage Range . . . . . . . . 0V to 5.5V
Operating Junction Temperature . . . . . . . . . . 0
°
C to 125
°
C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300
°
C
Note: 1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
D Package:
Thermal Resistance Junction-to-Ambient, θ
JA
. . . . . . 120°C/W
DW Package:
Thermal Resistance Junction-to-Ambient, θ
JA
. . . . . . 95°C/W
PWP Package:
Thermal Resistance Junction-to-Ambient, θ
JA
. . . . . . 139°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x θ
JA
).
The θ
JA
numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
1
IMP5
IMP
5
1
1
1
1
5
5
www.ds-imp.com.cn Daily Silver IMP