Key Features
◆
Ultra-Fast response for Fast-20 SCSI applications
◆
35MHz channel bandwidth
◆
3.3V operation
◆
Less than 3pF output capacitance
◆
Sleep-mode current less than 275µA
◆
Thermally self limiting
◆
No external compensation capacitors
◆
Implements 8-bit or 16-bit (wide) applications
◆
Compatible with active negation drivers
(60mA/channel)
◆
Compatible with passive and active terminations
◆
Approved for use with SCSI 1, 2, 3 and UltraSCSI
◆
Hot swap compatible
◆
Pin-for-pin compatible with LX5211 and
UC5606 (IMP5111)
◆
Pin-for-pin compatible with LX5212 and
UC5603/5613/5614 (IMP5112)
Block Diagrams
–
+
Current
Biasing
Circuit
Thermal
Limiting
Circuit
24mA Current
Limiting Circuit
Term Power
DATA OUTPUT
PIN DB (0)
1 of 9 Channels
DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
1.4V
2.85V
5111/5112_01.eps
9-Line SCSI T
9-Line SCSI T
er
er
minat
minat
or
or
– 35MHz Channel Bandwidt
– 35MHz Channel Bandwidt
h
h
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family
of high-performance SCSI terminators that deliver true UltraSCSI per-
formance. The BiCMOS design offers superior performance over first
generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator termi-
nator approach. The bandwidth of terminators based on the older
regulator/resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required. The IMP architecture
eliminates the external output compensation capacitor and the need
for transient output capacitors while maintaining pin compatibility
with first generation designs. Reduced component count is inherent
with the IMP5111/5112.
The IMP5111/5112 architectur e tolerates marginal system designs. Akey
improvement offered by the IMP5111/5112 lies in its ability to insure
reliable, err or-fr ee communications even in systems which do not adhere
to recommended SCSI hardware design guidelines, such as improper
cable lengths and impedance. Frequently, this situation is not controlled
by the peripheral or host designer.
For portable and configurable peripherals, the IMP5111/5112 can be
placed in a sleep mode with a disconnect signal. Quiescent current is less
than 275
µ
A when disabled. When disabled, the outputs are in a high
impedance state with output capacitance less than 3pF.
1
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
D
ATA
C
OMMUNICATIONS
1
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
D
ATA
C
OMMUNICATIONS
Daily Silver IMP www.ds-imp.com.cn
2
Pin Configuration
Ordering Information
Absolute Maximum Ratings
1
8T2
1T7
DW Package
9T3
7T1 10 T4
6DISCONNECT* 11 V
TERM
5GND 12 HEAT SINK/GND
4HEAT SINK/GND 13 HEAT SINK/GND
3T9 14 NC
2T8 15 T5
16 T6
5111/5112__02.eps
IMP5111
IMP5112
*DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
SO-16
*DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
12T2
1T7
PW Package
13 T3
7HEAT SINK/GND 18 HEAT SINK/GND
8HEAT SINK/GND 17 HEAT SINK/GND
9HEAT SINK/GND 16 NC
10DISCONNECT* 15 V
TERM
11T1 14 T4
6HEAT SINK/GND 19 HEAT SINK/GND
5GND 20 HEAT SINK/GND
4NC 21 NC
3T9 22 NC
2T8 23 T5
24 T6
5111/5112_02a.eps
IMP5111
IMP5112
TSSOP-24
rebmuNtraPegnaRerutarepmeTegakcaP
PDC1115PMI0° 521otC °COScitsalPnip-61
TPDC1115PM
I0
°
521otC
°
CO
ScitsalPnip-61,leeRdnaepaT
PWPC1115PMI0° 521otC °CPOSSTcitsalPnip-42
TPWPC1115PMI0° 521otC °CPOSSTcitsalPnip-42,leeRdnaepaT
PDC2115PMI0° 521otC °COScitsalPnip-61
TPDC2115PMI0° 521otC °COScitsalPnip-61,leeRdnaepaT
PWPC2115PM
I0
°
521otC
°
CP
OSSTcitsalPnip-42
TPWPC2115PMI0° 521otC °CPOSSTcitsalPnip-42,leeRdnaepaT
3ta.10t_2115/1115
Thermal Data
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Regulator Output Current . . . . . . . . . . . . . . . . . . 0.4A
Operating Junction Temperature
Plastic (DP, PWP Packages) . . . . . . . . . . . . . . . 150°C
Note: 1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 °C to 150°C
Lead Temperature (Soldering, 10 seconds) . . . . . 300
°
C
DP Package:
Thermal Resistance Junction-to-Leads, θ
JL
. . . . . . . . 20°C/W
Thermal Resistance Junction-to-Ambient, θ
JA
. . . . . . 50°C/W
PW Package:
Thermal Resistance Junction-to-Leads, θ
JL
. . . . . . . . 27°C/W
Thermal Resistance Junction-to-Ambient, θ
JA
. . . . . . 100°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x θ
JA
).
The θ
JA
numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
IMP5
IMP5
1
1
1
1
1/5
1/5
1
1
1
1
2
2
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