The IMP16C554
i
s
a
un
i
ver
s
al
a
s
y
n
c
hronous re
c
e
i
v
er and
transmitter with 16 byte transmit and receive FIFO. A
programmable baud rate generator is provided to select
trans
mi
t and
re
ce
iv
e c
lo
ck ra
tes
f
rom
50Hz t
o
1.
5M
Hz.
The IMP16C554
i
s
an
i
m
proved ver
s
i
on of
t
he
IMP16C550
UART with hi gher operating speed and lower acces s time.
The IMP16C554 on board status registers provides the
error conditions, type and status of the transfer operation
be
i
ng per
f
o
r
m
ed.
I
n
c
l
uded
i
s
c
o
m
p
l
e
t
e
M
O
D
E
M
c
on
t
rol
capability, and a processor interrupt system that may be
software tailored to the user’s requirements. The
IMP16C554 provi
des
in
ternal
l
oop
-bac
k c
ap
abil
it
y
for on
board diagnostic test i ng.
The IMP16C554 is fabricated in an advanced 1.2u CMOS
process to achieve low drain power and high speed
16 byte receive FIFO with error flags
Modem control signal (CTS*, RTS*, DSR*, DTR*,
RI* ,CD*)
Programmable character lengths(5,6,7,8)
E
ven,
odd,
or no
par
it
y
bit
genera
ti
on and det
ec
ti
on
Status report register
Independent
tra
ns
mi
t
and re
ce
iv
e con
trol
TLL
c
o
m
p
a
t
i
b
l
e
i
npu
t
s.
ou
t
pu
t
s
Software compatible with Ei8250, 1Ei16C550
460.8kHz transmit/receive operation with 7.372
MHz crystal or external cl ock source
1
IMP16C554
IMP16C554
Data Communications
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DSRA•
CTSA•
DTRA•
VCC
RTSA•
INTA
CSA•
TXA
IOW•
TXB
CSB•
INTB
RTSB•
GND
DTRB
CTSD•
DSRB•
DSRA•
CTSA•
DTRA•
VCC
RTSA•
INTA
CSA•
TXA
IOW•
TXB
CSB•
INTB
RTSB•
GND
DTRB
CTSD•
DSRD•
CTSD•
DTRD•
GND
RTSD•
INTD
CSD•
TXD
IOR•
TXC
CSC•
INTC
RTSC•
VCC
DTRC•
CTSC•
DSRC•
DSRD•
CTSD•
DTRD•
GND
RTSD•
INTD
CSD•
TXD
IOR•
TXC
CSC•
INTC
RTSC•
VCC
DTRC•
CTSC•
CDB•
RIB•
RXB•
VCC
NC
A2
A1
A0
XTAL1
XTAL2
ERSET
RXRDY���
TXRD•
GND
RXC
RIC•
CDC•
DSBS•
CDS•
RIB•
RXB•
VCC
A2
A1
A0
XTAL1
XTAL2
RESET
GND
RXC
RIC•
CDC•
DSRC•
CDA•
RIA•
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID•
CDO•
CDA•
RIA•
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
RXD
RID•
COD•
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
16C554
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
16C554
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64-PIN QFP68-PIN PLCC
IMP
IMP
requirements.
Description
Key Features
Pin Configuration
Quad Universal Asynchronous
Receiver/Transmitter
(UART)
with FIFO's
www.ds-imp.com.cn Daily Silver IMP
SYMBOL DESCRIPTION
symbol pin Signal Type Pin Description
D0-D7
RX A-B
RX C-D
TX A-B
TX C-D
CS*A-B
CS*C-D
XTAL1
XTAL2
LOW*
GND
GND
IOR*
5-66
7.29
41.63
17.19
51.53
16.20
50.54
35
36
18
6.23
40.57
52
I/O
I
O
I
I
O
I
O
I
Bi-directional data bus. Eight bit, three state data bus to
transfer information to or from the CPU. Do is the least
significan t bit of the data b us and the first s erial data bit to be
received or transmitted.
Serial data input. The serial information (data) received from
serial port to IMP16C554 receive input circuit . A mark (high)
is lo
gic o
ne and
a spa
ce (
low
)is
logi
c zer
o. Du
rin
g the l
ocal
loopback mode the RX input is disabled from external
connection and to the TX output internally.
Serial data output. The serial data is transmitted via this pin
with additional start, stop and parity bits. The TX will be held
in mark(high) state during reset, local loopback mode or
when the transmitter is disable d.
Chip select. (active low) A low at this pin enables the
IMP16C554/
CPU
dat
a tran
sfer
oper
atio
n. Ea
ch UART
sec
tions
of
the IMP16C5
54 c
an be acc
essed in
depe
ndentl
y.
Crystal input 1 or external clock input. A crystal can be
connected to this pin and XTAL2 pin to utilize the internal
oscillator circuit. An external clock can be used to clock
internal circuit and baud rate generator for custom
transmission rates.
Crystal input 2 or buffered clock output. See XTAL1.
Write strobe.(active low)A low on this pin will transfer the
contents of the CPU data bus to the addressed register.
Signal and power ground.
Read strobe.(active low)A low level on this pin transfers the
contents of the IMP16C554 data bus to the CPU.
2
IMP16C554
IMP16C554
www.ds-imp.com.cn Daily Silver IMP