Data Communications
IMP16C550
IMP16C550
Data Communications
1
Key Features
Universal Asynchronous
Receiver/Transmitter
(UART)with 16-BYTE FIFO's
•5V Operation
• Full duplex asynchronous receiver and transmitter
• Easily interfaces to most popular micro-
processors
• Adds or deletes standard asynchronous
communication bits (start, stop, and parity) to or
from a serial data stream
• Independently controlled transmitter, receiver,
line status, and data set interrupts
• Programmable baud rate generator allows
division of any input clock by 1 to (2
16
-1) and
generates the internal 16 x clock
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR,
DTR, RI,and DCD)
• Fully programmable serial interface
characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
• False start bit detection
• Complete status reporting capabilities
• Tri-State® TTL drive capabilities for bi-
directional data bus and control bus
• Line break generation and detection
• Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity overrun, and framing error simulation
• Fully prioritized interrupt systems controls
• 16 byte FIFO for reduced CPU overhead
The IMP16C550 Universal Asynchronous Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
The UART performs serial to parallel conversion on
data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversions on data charac-
ters received from the CPU. The CPU can read the complete
status of the UARTat any time during the functional operation.
Status information reported includes the type and condition of
the transfer operation being performed by the UART, as well
as any error conditions (party, overrun, framing, or break
detect).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
M
P
1
6
C
5
5
0
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2•
BAUDOUT•
XTAL1
XTAL2
DOSTR•
VSS
VCC
RI•
DCD•
DSR•
CTS•
MR
OUT1•
DTR•
RTS•
OUT2•
INTRPT
RXRDY•
A0
A1
A2
ADS•
TXRDY•
DDIS
DISTR
DISTR•
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2•
BAUD-
OUT•
MR
OUT1•
DTR•
RTS•
OUT2•
NC
INTRPT
RXRDY•
A0
A1
A2
XTAL1
XTAL2
DOSTR•
DOSTR
VSS
NC
DISTR•
DISTR
DDIS
TXRDY•
ADS•
D4
D3
D2
D1
D0
NC
VCC
RI•
DCD•
DSR•
CTS•
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
IMP16C550
40-PIN DIP
44-PIN PLCC
36 N.C.
35 RESET
34 OP1
•
33 DTR
•
32 RTS
•
31 OP2
•
30 INT
29 RXRDY
•
28 A0
27 A1
26 A2
25 N.C.
N.C. 1
D5 2
D6 3
D7 4
RCLK 5
N.C. 6
RX 7
TX 8
CS0 9
CS1 10
CS2
•
11
BAUDOUT
•
12
48 N.C.
47 D4
46 D3
45 D2
44 D1
43 D0
42 VCC
41 RI
•
40 CD
•
39 DSR
•
38 CTS
•
37 N.C.
N.C. 13
XTAL1 14
XTAL2 15
-IOW 16
IOW 17
GND 18
IOR
•
19
IOR 20
N.C. 21
DDIS
•
22
TXRDY
•
23
AS 24
48-PIN TQFP
IMP16C550
General Description
Pin
Configuration
I
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T
he
IMP
16C
5
5
0
i
s
an
en
h
an
c
e
d
v
e
r
s
io
n
o
f
t
he
IMP
1
6C
4
50 U
n
i
v
e
r
s
a
l
A
s
yn
c
h
r
onou
s
R
e
c
e
i
v
e
r
/
Transmitter (UART). The improved specifications
ensur
e easy
int
erfa
ce w
ith exi
sti
ng
microprocessors systems with DMA controller.
F
uncti
onall
y i
denti
cal to t
he IMP
16C450 o
n powe
r
up
(in
Char
acter
Mode
) t
he IMP16C
550
can
be
configured into an alternate mode(FIFO mode) to
relie
ve the C
PU of
exces
sive
softw
are
ove
rhead
due to interrupts.
In FIF
O m
ode, in
tern
al
FIFO
’s a
re ac
tivat
ed
allowing 16 bytes (plus 3 bits of error data per byte
in the RCVR F
IFO
) to be
stor
ed in both
rece
ive
and
tr
ansm
it mode
s. All
the
logi
c is
on ch
ip t
o
minimize system overhead and maximize system
ef
fic
ienc
y. T
wo
FIFO
co
ntro
l pin
s h
ave
been
added
to allow signaling of DMA transfers.
The UA
RT pe
rfo
rms
ser
ial-
to-p
ara
lle
l co
nve
rsion
on data
char
acte
rs
rec
eived f
rom
a perip
hera
l
de
vic
e or a
MOD
EM, an
d p
ara
llel-
to-
ser
ial
conversion on data characters received from the
CPU. The CPU can read the complete status of
the UART at any time during the functional
operation. Status information reported includes
the type and condition of the transfer operations
being performed by the UART, as well as any error
conditions (parity, overrun, framing, or break
interrupt).
The UART includes a programmable baud rate
generator that is capable of dividing the timing
reference clock input by divisors of 1 to (2
16
-1),
and
p
r
odu
c
i
ng
a 16
x
c
l
o
c
k
to d
r
ive
t
he
in
t
e
r
n
a
l
transmitter logic. Provisions are also included to
use this 16x clock to drive the receive logic. The
UART has complete MODEM-control capability,
and a processor interrupts system. Interrupts can
be programmed to the user’s requirements,
minimizing the computing required to handle the
communications link. UART is designed to work
either in a polled or an interrupt driven
environment selected by software.
The UART is fabricated using IMP’s advanced
double metal CMOS process.
FIGURE 1 – IMP16C550 General System Configuration
SYSTEM
PROCESSOR
DATA BUS
BUFFER
RECEIVER
SECTION
TRANSMITTER
SECTION
MODEM
CONTROL AND
STATUS LOGIC
INTERRUPT
ENABLE AND
CONTROL
SELECT AND
CONTROL
LOGIC
PARALLEL I/O
INTERFACE
MEMO"RY
INTERRUPT
A0
A1
A2
SERIAL DATA
IN
SERIAL DATA
OUT
MODEM CONTROL
FUNCTIONS
TO/FROM MODEM
OR DATA SET
TO/FROM
PERIPHERAL
MODEM OR
DATA SET
CONTROL BUS
DATA BUS
ADDRESS BUS
IMP16C550
IMP16C550
2
Description
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