• 3.3 or 5V Operation
• Full duplex asynchronous receiver and
transmitter
�� Easily interfaces to most popular
microprocessors
• Adds or deletes standard asynchronous com-
munication bits (start, stop, and parity ) to or
from a serial data stream
• Independently controlled transmitter, receiver,
line status, and data set interrupts
• Programmable baud rate generator allows
division of any input clock by 1 to (2
16
-1) and
generates the internal 16 x clock
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• Fully programmable serial interface characteris
tics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
• False start bit detection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
M
P
1
6
C
4
5
0
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2•
BAUDOUT•
XTAL1
XTAL2
DOSTR•
DOSTR
VSS
VCC
RI•
DCD•
DSR•
CTS•
MR
OUT1•
DTR•
RTS•
OUT2•
INTRPT
NC
A0
A1
A2
ADS•
CSOUT
DDIS
DISTR
DISTR•
39
38
37
36
35
34
33
32
31
30
29
7
8
9
10
11
12
13
14
15
16
17
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2•
BAUDOUT•
MR
OUT1•
DTR•
RTS•
OUT2•
NC
INTRPT
NC
A0
A1
A2
40-PIN DIP
44-PIN PLCC
36 N.C.
35 RESET
34 OP1
•
33 DTR
•
32 RTS
•
31 OP2
•
30 INT
29 N.C.
28 A0
27 A1
26 A2
25 N.C.
N.C. 1
D5 2
D6 3
D7 4
RCLK 5
N.C. 6
RX 7
TX 8
CS0 9
CS1 10
CS2
•
11
BAUDOUT
•
12
48 N.C.
47 D4
46 D3
45 D2
44 D1
43 D0
42 VCC
41 RI
40 DCD
•
39 DSR
•
38 CTS
•
37 N.C.
N.C. 13
XTAL1 14
XTAL2 15
IOW
•
16
IOW
•
17
GND 18
IOR
•
19
IOR 20
N.C. 21
DDIS
•
22
CSOUT 23
AS
•
24
48-PIN TQFP
• Complete status reporting capabilities
• Tri-State® TTL drive capabilities for bi-direc
tional data bus and control bus
• Line break generation and detection
• Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity overrun, and framing error simulation
• Fully prioritized interrupt systems controls
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
The UART performs serial to parallel conversion
on data characters
received from a peripheral
device or a MODEM, and parallel-to-serial
conversions on data characters received from the
CPU. The CPU can read the complete status of the
UART at any time during the functional operation.
Status information reported includes the type and con-
dition of the transfer operation being performed by the
UA
RT
, as well as any error conditions (parity
, overrun,
•
5V Operation
•Full duplex asynchronous receiver and
transmitter
•
Easily in
t
erfa
c
es to most popular
mic
ropro
cessors
•
Adds or deletes standard asynchronous com-
munication bits (start, stop, and parity ) to or
from a serial data stream
•Independently controlled transmitter
, receiver,
line status, and data set interrupts
•
Programmable baud rate generator allows
division of any input clock by 1 to (2
16
-1) and
generates the internal 16 x clock
•
Independent receiver clock input
•MODEM control functions (CTS, RTS, DSR,
DTR, RI, and DCD)
•Fully programmable serial interface characteris
tics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
•False start bit detection
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2•
BAUDOUT•
MR
OUT1•
DTR•
RTS•
OUT2•
NC
INTRPT
NC
A0
A1
A2
XTAL1
XTAL2
DOSTR•
DOSTR
VSS
NC
DISTR•
DISTR
DDIS
CSOUT
ADS•
D4
D3
D2
D1
D0
NC
VCC
RI•
DCD•
CDSR•
CTS•
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
IMP16C450
40-PIN DIP
44-PIN PLCC 48-PIN TQFP
IMP16C450
• Complete status reporting capabilities
• Tri-State® TTL drive capabilities for bi-direc
tional data bus and control bus
• Line break generation and detection
• Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity overrun, and framing error simulation
• Fully prioritized interrupt systems controls
IMP
16C450
Universal
Asynchronous
Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
The UART performs serial to parallel conversion
on data characters
received from a peripheral
device or a MODEM, and parallel-to-serial
conversions on data characters received from the
CPU. The CPU can read the complete status of the
UART at any time during the functional operation.
Status information reported includes the type and con-
dition of the transfer operation being performed by the
UART, as well as any error conditions (parity, overrun,
framing, or break detect).
IMP16C450
IMP16C450
Data Communications
1
Key Features
General
Description
Universal Asynchronous
Receiver/Transmitter
(UART)
I
Pin Configuration
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The IMP16C450 UART performs serial-to-parallel
conversion on data characters received from a
peripheral device or a MODEM, and
parallel-to-serial conversion on data
characters received from the CPU. The CPU
can read the complete status of the UART at
any time during the functional operation.
Status information reported includes the type
and condition of the transfer operations being
performed by the UART, as well as any error
conditions (parity, overrun, framing, or break
interrupt).
The UART includes a programmable baud
rate generator that capable of dividing the
timing reference clock input by divisor of 1 to
(2
16
-1), and producing a 16 x clock to drive the
internal transmitter logic. Provisions are also
included to use this 16 x clock to drive the
receiver logic. The UART has complete
MODEM-control capability, and a processor
interrupts system. Interrupts can be
programmed to the user’s the requirements,
minimizing the computing required to handle
the comm unications link. UART is des igned to
work either in a polled or an interrupt driven
environment selected by software.
The UA
RT
is fab
ric
ated u
sing
IMP’s
advanced double metal CMOS process.
FIGURE 1 – IMP16C450 General System Configuration
SYSTEM
PROCESSOR
DATA BUS
BUFFER
RECEIVER
SECTION
TRANSMITT
ER
SECTION
MODEM
CONTROL
AND
STATUS
LOGIC
INTERRUPT
ENABLE
AND
CONTROL
SELECT AND
CONTROL
LOGIC
PARALLEL I/O
INTERFACE
MEMORY
INTERRUPT
A0
A1
A2
SERIAL DATA
IN
SERIAL
DATA
OUT
MODEM CONTROL
FUNCTIONS
TO/FROM MODEM
OR DATA SET
TO/FROM
PERIPHERAL
MODEM OR
DATA SET
CONTROL
BUS
DATA BUS
ADDRESS BUS
IMP16C450
IMP16C450
2
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