DS-00001-10 rev8I 2020-02-10
© 2020 X-REL Semiconductor
AVAILABLE FUNCTIONALITIES FOR EACH PACKAGING FAMILY
Supported converter architectures for given packaging option
Packaging Configurations with OCPMode=1
Tunable clock with external R or C or possible synchronization on an external clock
Internal saw-tooth resistor
Adjustable saw-tooth slope
Available PGood output flag
Possible automatic synchronous/asynchronous mode transition (with or without pulse skipping)
Possible “synchronous only” mode (except during startup)
Possible pulse skipping in steady state (i.e. after startup period)
Adjustable pulse skipping threshold
Low power mode (VDD=4V) availability with possible bypass of the internal LDO by an external 5V
Adjustable soft-start slope or possible tracking
Possible over current protection using the OCS pin
3
Possible adjustable limitation of the max duty cycle
4,5
Separate GND and PGND pins
Separate VDD and PVDD pins
Compact packaging (number of pins)
Packaging Configurations with OCPMode=0
Tunable clock with external R or C or possible sync on an external clock
Internal saw-tooth resistor
Adjustable saw-tooth slope
Available PGood output flag
Possible turn off of the LDrv(ADrv) output pad if not used for power saving
6
Possible pulse skipping in steady state (i.e. after startup period)
Adjustable pulse skipping threshold
Low power mode (VDD=4V) availability with possible bypass of the internal
LDO by an external 5V
Adjustable soft start slope or possible tracking
Possible over current protection using the OCS pin3
Possible adjustable limitation of the max duty cycle4
,
5
Separate GND and PGND pins
Separate VDD and PVDD pins
Compact packaging (number of pins)
1
See “Saw-tooth signal generation” and “PWM signal generation” in section “Theory of Operation”.
2
In this packaging configuration current mode control can be achieved by the addition of few external components.
3
This is the main overcurrent protection, based on a sense resistor from the low-side switch (or asynchronous rectifier) to PGND. A
second short circuit protection associated to the DCLimit terminal is also present. The short-circuit protection related to DCLImit is
based in detecting if the error amplifier is always working on its linear regime. This second protection is only efficient for strong short-
circuit conditions. For weak over current values, it will not trig or very lately, so that the power part could be damaged if the main short
circuit protection is not active.
4
Internally, DCLimit is set to 2/5VDD. Depending on the clock period and the saw-tooth slope, the maximum duty cycle can be limited
intrinsically. The range is however quite limited. Also, the saw-tooth slope and frequency are usually set by loop gain and stability con-
straints. Therefore, we consider here only the possibility of an independent control of the maximum duty-cycle, based on the availability
of the DCLimit pin.
5
DCLimit functionality is also used as a short-circuit protection. See “Over-current protection” in the “Theory of Operation” section.
6
LDrv is OFF when OCPMode and AsyncEnbl are both low.