FEDL620Q416A-01
Issue Date: Jan. 5, 2017
ML620Q416A/Q418A
Ultra Low Power 16-bit Microcontroller
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■ GENERAL DESCRIPTION
This LSI family is a high-performance 16bit CMOS microcontroller into which rich peripheral circuits, such as
synchronous serial port, UART, I
2
C bus interface, supply voltage level detect circuit, RC oscillation type A/D
converter, successive approximation type A/D converter, and LCD driver are incorporated around 16bit CPU
nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by
3-stage pipe line architecture parallel processing. The Flash ROM that is installed as program
memory achieves low-voltage low-power consumption operation (read operation) is most suitable
for battery-driven applications. And, this LSI has a writable data flash memory area by the
software and a function to re-writing program area from software.
The on-chip debug function that is installed enables program debugging and programming.
■ FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system: 16bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division,
bit manipulations, bit logic operations, jump, conditional jump, call return stack
manipulations, arithmetic shift, and so on.
− Build-in On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
62.5ns (@16 MHz system clock)
• Built-in coprocessor for multiplication, division, and multiply-accumulate operations
− Signed or unsigned operation setting
− Multiplication: 16bit × 16bit (operation time 4 cycles)
− Division: 32bit / 16bit (operation time 8 cycles)
− Division: 32bit / 32bit (operation time 16 cycles)
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
• Internal memory
− Supports ISP function (re-writing the program memory area by software)
− Number of segments
Product
name
Flash memory
SRAM
Program area*
Data area
ML620Q416A
128KB (64K × 16bit)
4KB (2K × 16bit)
16KB (8K × 16bit)
ML620Q418A
256KB (128K × 16bit)
4KB (2K × 16bit)
16KB (8K × 16bit)
*: including 1KB of unusable test area
• Interrupt controller (INTC)
− 1 non-maskable interrupt sources (Internal source: 1)
− 46 maskable interrupt sources (Internal sources: 38, External sources: 8)
− Software interrupt (SWI): maximum 64 sources
− External interrupt and comparator allow edge selection and sampling selection
− Priority level (4-level) can be set for each interrupt
ML620Q416A/Q418A
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• Time base counter (TBC)
− Low-speed time base counter × 1 channel
• 1 kHz Timer
− 10 Hz / 1 Hz interrupt function
• Timers (TMR)
− 8 bit × 8 channels
(Timer0-7: 16bit × 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7)
− Selection of one shot timer mode is possible
− External clock can be selected as timer clock.
• Function Timers (FTM)
− 16bit × 4 channels
− Equipped with the timer/capture/PWM functions using a 16bit counter
− An event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the
timer (however, the minimum pulse width of pin input is timer clock 3)
− 1 to 64 dividing of LSCLK/OSCLK/HSCLK/external input selectable as timer clock
− Two types of PWM with the same period and different duties and complementary PWM with the dead time
set can be output.
• Real Time Clock (RTC)
− 3 channels (99 years calendar, alarm, revision of the clock)
• Watchdog timer (WDT)
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)
• Synchronous serial port (SSIOF/ SSIO)
− without FIFOs (SSIO) : 1 channel
− with 16-byte transmits and receives FIFOs (SSIOF) : 1 channel
− Master/slave are selectable
− LSB first/MSB first are selectable
− Clock polarity (data out at rising edge and data in at falling edge/data out at falling edge and data in at rising
edge) selectable
− 8bit length/16bit length are selectable
− Initial clock level (High start/Low start) selectable
− supports slave-select signal (only SSIOF)
• UART (UARTF/ UART)
− without FIFOs (UART) : 1channel
− with 16-byte transmits and receives FIFOs (UARTF) : 2channel
− Full duplex buffer system
− Communication speed: Settable within the range of 2400bps to 460800bps.
− Programmable interface (data length, parity, stop bits are selectable)
• I
2
C bus interface (I
2
CF/ I
2
C)
− without FIFOs(I
2
C) :1 channel
− with 16-byte transmits and receives FIFOs(I
2
CF): 2 channel
− Master/Slave function
− Fast mode (400 kHz), standard mode (100 kHz)