Video Module Interface (VMI ) for ICs

Author: Keith Jack

Introduction

VMI was developed in cooperation with several multimedia

IC companies in order to standardize the video interfaces

between devices such as MPEG decoders, NTSC/PAL

decoders, and GUI accelerators. It is primarily based on the

output interface and timing of the Philip's SAA7111

NTSC/PAL decoder.

Video Data Format

An 8-bit 4:2:2 YCbCr interface is normally used, similar to

that used by the BT.656 parallel interface. However, the EAV

and SAV sequen ce s that BT.656 uses are not presen t.

The 4:2:2 YCbCr data is multiplexed into an 8-bit stream:

, etc. Figures 1 and 2 illustrate the

format for 525/60 and 625/50 video systems, respectively,

using 8-bit YCbCr data.

The stream of active data words always begins with a Cb

sample. In the multiplexed sequence, the co-sited samples

(those that correspond to the same point on the picture) are

grouped as Cb, Y, Cr.

VMI does not define a specific pixel clock rate. However,

most rec tan gular pi xe l appli catio ns sampl e ea ch line of vide o

at 13.5MHz, generating 720 active samples of 24-bit 4:4:4

YCbCr data, as shown in Figures 3 and 4. This is converted

to 16-bit 4 :2:2 YC bCr dat a, resu lting i n 720 ac tive sam ples of

Y per line, and 360 active samples each of Cb and Cr per

line. The Y data and the CbCr data are multiplexed, and the

13.5MHz sample clock rate is increased by two to 27MHz.

VMI also does not define any horizontal or vertical blanking

intervals, using instead a programmable blanking signal

(VACTIVE). For most rectangular pixel applications, the ver-

tical blanking intervals will be as shown in Figures 5 and 6.

Note that active resolutions other than 720 x 486 and 720 x

576 may be supported (effectively cropping the image) by

adjusti ng the tim in g of VACTIVE.

Square Pixel Variation

A variation using square pixels may also be used. Instead of

a 27MHz clock, a 24.54MHz clock is used for 525/60 video

systems (640 x 480 active resolution), and a 29.5MHz clock is

used for 625/50 video system s (768 x 57 6 active res olution).

FIGURE 1. TYPICAL VMI 8-BIT DATA FORMAT FOR RECTANGULAR PIXEL 525/60 VIDEO SYSTEMS

CO-SITED

START OF DIGITAL ACTIVE LINE

NEXT LINE

VACTIVE CONTROL SIGNAL

CO-SITED

BLANKING

1716

1440

DIGITAL

VIDEO

STREAM

No. AN9738 September 199 7 Intersil Multimedia

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

Application Note 9738

Figures 7 and 8 illustrate the data format, Figures 9 and 10

illustrate the typical horizontal timing relationships, and Fig-

ures 11 and 12 show the typica l vertical blanki ng intervals.

16-Bit YCbCr Variation

Although not a part of the VMI specification, a variation using

16-bit 4:2:2 YCbCr data is common, as shown in Figures 13

and 14. In thi s instance, t he P IXCLK signal is one-half the nor-

mal clock rate: 13.5MHz, 12.27MHz (square pixel 525/60 video

systems) or 14.75MHz (square pixel 625/50 video systems).

Video Timing Signals

In addition to the pixel data, there are four video timing sig-

nals, consisting of VREF, HREF, VACTIVE, and PIXCLK. To

support video sources that do not generate a line-locked

clock, a Data Valid signal (DVALID) is also commonly used.

VREF and HREF can be considered to be VSYNC and

HSYNC signals, respectively. If HREF is high during the fall-

ing edge of VREF, the field is odd. If HREF is low during the

falling edge of VREF, the field is even. Thus, even/odd field

detectio n is d one using the trai ling e dge of VREF, rather tha n

the leading edge, as with most video systems. Figures 15

and 16 illus trat e the HREF an d VREF timi ng for 5 25/60 and

65/50 video systems, respectively.

VACTIVE can be c ons id ere d a bl ank ing signal , a nd indicate s

that valid pixel data is being transmitted across the YCbCr

bus. If a DVALID signal is also used, valid pixel data is

present when both VACTIVE and DVALID are asserted.

For 8-bit YCbCr interfaces, PIXCLK is a 2x pixel clock. For

16-bit YCbCr interfaces, PIXCLK is a 1x pixel clock.

FIGURE 3. TYPICAL VMI HORIZONT AL TIMING RELA TIONSHIP

FOR RECTANGULAR PIXEL 52 5/60 VIDEO SYSTEMS

FIGURE 4. TYPICAL VMI HORIZONT AL TIMING RELATIONSHIP

FOR RECTANGULAR PIXEL 625/50 VIDEO SYS TEMS

FIGURE 2. TYPICAL VMI 8-BIT DATA FORMAT FOR RECTANGULAR PIXEL 625/50 VIDEO SYSTEMS

CO-SITED

START OF DIGITAL ACTIVE LINE

NEXT LINE

VACTIVE CONTROL SIGNAL

CO-SITED

BLANKING

1728

1440

DIGITAL

VIDEO

STREAM

T = 1/13.5MHz

16T

50% SYNC

LEVEL

BLANKING

138T

(720-857)

DIGITAL ACTIVE LINE

720T

(0-719)

TOTAL LINE

858T

(0-857)

T = 1/13.5 MHz

12T

50% SYNC

LEVEL

BLANKING

144T

(720-863)

DIGITAL ACTIVE LINE

720T

(0-719)

TOTAL LINE

864T

(0-863)

Application Note 9738