DDR3 SDRAM MEMORY
3D3D16G72WB2768
Datasheet
DDR3 SDRAM Memory
3D3D16G72WB2768 3D PLUS SA reserves the right to cancel product or specifications without notice
3DDS-0768-REV 3 APRIL 2021
Page: 1/ 15
FEATURES
Unbuffered DDR3 “SO-DIMM” SDRAM 72b in
a 223 BGA package ( pitch of 1 mm) : 27.20x18x4.4mm
Organized as a single bank of 256Mx72 bits
16Gb for data on a 64-bit bus and 2Gb for ECC
VDD/VDDQ = 1.5V±0.075V
DDR3L support VDD/VDDQ= 1.35V
Support ECC error detection and correction
Fully differential clock inputs (CK, CK#) operation
Programmable CAS Latency
Sequential & Interleaved Burst type available both
for 8 & 4 with BC
Selectable BC4 or BL8 on the fly
On Die Termination (ODT)
Auto Refresh and Self Refresh
High Temperature Self-Refresh rate enable
ZQ calibration for DQ drive and ODT
Single rank
Fly-by topology
Terminated control, command and address buses
RESET pin for initialization and reset function
Fast data transfer rate available : PC3-6400, PC38500
and PC3-10600
Industrial and Military temperature range.
Leaded solder balls
Refresh time of 8192-cycle at TC temperature range:
o 64ms at 55°C to 85°C
o 32ms at 85°C to 95°C
o 16ms at 95°C to 105°C
o 8ms at 105°C to 125°C
Applications:
- Embedded Systems
- Single board computers
- High performance computers
- Test Systems
DDR3 SDRAM MEMORY
3D3D16G72WB2768
Datasheet
DDR3 SDRAM Memory
3D3D16G72WB2768 3D PLUS SA reserves the right to cancel product or specifications without notice
3DDS-0768-REV 3 APRIL 2021
Page: 2/ 15
GENERAL DESCRIPTION
The 3D3D16G72WB2768 is a highly integrated module operating as a DDR3 SDRAM 72b SO-DIMM in a
BGA package. It is intended for use as main memory when installed in embedded systems.
It offers a memory density of 16Gbits with ECC on a 72 bits data bus in a single rank of 256Mbx72 high
speed memory array. It is based on 5 dies achieving high speed double-data-rate transfer rates of up to
1333 Mb/sec/pin for general applications. The module is designed to comply with the following key DDR3
SO-DIMM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) On Die
Termination (4) programmable driver strength data, (5) seamless BL4 access.
All the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are
synchronized with a pair of bidirectional differential data strobes (DQS and DQS#) in a source synchronous
fashion. The address bus is used to convey row, column and bank address information in a RAS# and
CAS# multiplexing style.
The 16Gb DDR3 device operates with a single power supply: 1.5V VDD (or 1.35V in DDR3L mode).
This device is ideal for high density memory applications that require high speed transfer and compatibility
with standard processors, DSP or FPGAs.