Xilinx Answer 72702 – Interrupt Debug Guide 1

Xilinx Answer 72702

UltraScale and UltraScale+ PCIe Interrupt debug guide

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Introduction

This document provides the steps involved to initiate Legacy, MSI and MSI-x interrupts with different IP cores targeting

UltraScale and UltraScale+ devices. (Xilinx Answer 58495) provides the theoretical background and the steps to initiate

Legacy and MSI interrupts with the 7 Series Integrated block IP core.

Legacy Interrupts

Steps to initiate Legacy interrupts

The following steps are involved in generating Legacy interrupts:

1. Make sure the ‘Interrupt Disable’ bit in the Command Register is not set in the endpoint

2. Enable AXISTEN_IF_ENABLE_RX_MSG_INTFC in the IP GUI

3. Drive the interrupt ports

All of the steps mentioned above are applicable to the Integrated Block for PCIe IP in UltraScale/UltraScale+. With the

XDMA and AXI-Bridge subsystem IP cores, step 2 is done by default as these IP cores use the Integrated Block for PCIe

IP hierarchically and message interface options are set in this IP.

‘Interrupt Disable’ bit in Command Register

The ‘Interrupt Disable’ bit is bit10 in the Command Register of the configuration space. To make sure Legacy interrupts are

not disabled by the PCI express Integrated Block in the FPGA, this bit needs to be set to 1’b0.

Figure 1 Command register in Type 0 configuration space

Xilinx Answer 72702 – Interrupt Debug Guide 2

In a hardware design, this step can be implemented in the driver running on the host machine (or) using a hardware module

driving configuration management interface.

In simulation, the testbench in the Root Port model that comes with the generation of the IP, can be updated using the

TSK_TX_TYPE0_CONFIGURATION_WRITE task.

For example:

AXISTEN_IF_ENABLE_RX_MSG_INTFC

Legacy interrupts are generated as a message TLP with the message type set as “Assert_INTA” (or) “Deassert_INTA”. To

enable transmission of these messages, the “Config TX message Interface” and “Receive Message Interface” options need

to be enabled. This option is enabled in the IP configuration GUI by default. Make sure that this option is not deselected.

Drive the interrupt ports

After the steps mentioned in the previous section are completed, the design is ready to generate the interrupts. Refer to the

product guide of the target IP for the timing diagram of the interrupt signaling. It is also shown below for reference.

The figure below shows the timing diagram for the “Integrated block for PCI express” IP from (PG156). The same timing

diagram is applicable for both UltraScale and UltraScale+ devices.

Figure 2 Legacy Interrupt timing diagram for Integrated Block for PCIe IP (Ref: PG156, April 4, 2018)

The figure below shows the timing diagram for “DMA/Bridge subsystem” in “DMA” mode targeting UltraScale and

UltraScale+ devices and “AXI-Bridge” mode when targeting UltraScale+ devices. For an AXI-Bridge subsystem IP targeting

UltraScale devices, please refer to Table 1 for equivalent signals.