Development Board
EPC90142
Quick Start Guide
100 V Half-bridge with Gate Drive, Using EPC23101 and EPC2302
Revision 1.0
QUICK START GUIDE
EPC90142
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2
DESCRIPTION
The EPC90142 development board is a 100 V maximum device voltage,
65|A maximum output current, half bridge featuring the EPC23101
Integrated ePower™ FET and EPC2302 eGaN®FET. The purpose of this
development board is to simplify the evaluation process of the EPC23101
by including all the critical components on a single board that can be
easily connected into the majority of existing converter topologies.
The EPC90142 development board measures 2” x 2” and contains
one EPC23101 Integrated ePower™ FET in a half bridge conguration.
The board also contains all critical components and the layout supports
optimal switching performance. There are also various probe points to
facilitate simple waveform measurement and eciency calculation.
A block diagram of the circuit is given in gure 1.
For more information on the FETs associated with this board, please refer
to their datasheets available on EPC’s website: EPC23101 and EPC2302.
The datasheet should be read in conjunction with this quick start guide.
Table 1: Performance Summary (T
A
= 25°C) EPC90142
Symbol Parameter Conditions Min Nominal Max Units
V
DD
Gate Drive Input
Supply Range
7.5 12 V
V
IN
Bus Input Voltage
Range
(1)
80 V
I
OUT
Switch Node Output
Current
(2)
65 A
V
PWM
PWM Logic Input
Voltage Threshold
(3)
Input ‘High’
Input ‘Low’
3.5
0
5.5
1.5
V
V
Minimum ‘High’ State
Input Pulse Width
V
PWM
rise and
fall time < 10ns
50 ns
Minimum ‘Low’ State
Input Pulse Width
(4)
V
PWM
rise and
fall time < 10ns
200 ns
(1) Maximum input voltage depends on inductive loading, maximum switch node ringing
must be kept under 100 V for EPC23101.
(2) Maximum current depends on die temperature – actual maximum current is aected by
switching frequency, bus voltage and thermal cooling.
(3) When using the on board logic buers, refer to the EPC23101 datasheet when bypass-
ing the logic buers.
(4) Limited b
y time needed to ‘refresh’ high side bootstrap supply voltage.
EPC90142 development board
Back viewFront view
Figure 1: Block diagram of EPC90142 development board
V
Cntl
EN
U
1
L
1
LS
IN
HS
IN
V
Drv
R
nEV
V
DD
PWM
GND
C
IN
C
OUT
Q
2
V
DD
V
IN
150 k
GND
SW
GND
GND
V
DD
V
IN
V
IN
V
Boot
R
Boot
R
Boot
R
DRV
R
DRV
LG
OUT
Sync
boot
C
Boot
C
VDD
C
Drv
GND
Switch node
DC output
Logic and
dead-time
adjust
Logic
+
UVLO
+
POR
Level
shift
Delay
match
Output
driver
Enable
logic
Output
driver
EN
Logic
supply
EPC23101
EPC2302