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DS1016_01.3

December 2008 Data Sheet DS1016

p. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other

brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without

notice.

Features

■ Power Supply Margin and Trim Functions

• Trim and margin up to six power supplies

• Dynamic voltage control through I

• Four hardware selectable voltage proﬁles

• Independent Digital Closed-Loop Trim function

for each output

■ Analog Input Monitoring

• Six analog monitor inputs

• Differential input architecture for accurate

remote ground sensing

• 10-bit ADC for direct voltage measurements

■ 2-Wire (I

C/SMBus™ Compatible) Interface

• Readout of the ADC

• Dynamic trimming/margining control

■ Other Features

• Programmable analog circuitry

• Wide supply range, 2.8V to 3.96V

• In-system programmable through JTAG

• Industrial temperature range: -40°C to +85°C

• 32-pin QFNS (Quad Flat-pack, No lead, Saw-

singulated) package

, only 5mm x 5mm, lead-

free option

Description

Lattice’s Power Manager II ispPAC-POWR6AT6 is a

general-purpose power-supply monitoring and margin-

ing controller, incorporating in-system programmable

analog functions implemented in non-volatile E

CMOS

technology

. The ispPAC-POWR6AT6 device provides

six independent analog input channels to monitor up to

six power supply test points. Each of these input chan-

nels offers a differential input to support remote ground

sensing.

The ispPAC-POWR6AT6 incorporates six DACs for gen-

erating a trimming voltage to control the output voltage

of a power supply. The trimming voltage can be set to

four hardware selectable preset values (voltage proﬁles)

or can be dynamically loaded in to the DAC through the

C b

us. Additionally, each power supply output voltage

can be maintained within 1% tolerance across various

load conditions using the Digital Closed Loop Control

1. Use 32-pin QFNS package for all new designs. Refer to PCN

#13A-08 for 32-pin QFN package discontinuance.

Application Bloc

k Diagram

Power Supply

Margin/Trim

Control

6 Analog

Monitor Inputs

Interface

6 Analog

Trim Outputs

ADC

ispPAC-POWR6AT6

3.3V

2.5V

1.8V

POL#1

POL#2

POL#3

Other Board Circuitry

Trim

Vout

Trim

Vout

Trim

Vout

Trim

Vout

Trim

Vout

Trim

Vout

CPU

Bus

mode. The operating voltage proﬁle can be selected

using external hardware pins.

The on-chip 10-bit A/D converter can both be used to

monitor the V

MON

voltage through the I

C bus as well as

for implementing digital closed loop mode for maintain-

ing the output voltage of all power supplies controlled by

the monitoring and trimming section of the ispPAC-

POWR6AT6 device.

The I

C bus/SMBus interface allows an external micro-

controller to measure the voltages connected to the

MON

analog monitor inputs and load the DACs for the

generation of the trimming voltages of the external DC-

DC converters.

ispP

AC-POWR6AT6

In-System Programmable Power Supply

Monitoring and Margining Controller