Table 1. Errata and Information Summary
Erratum ID Erratum Title
ERR050143 CCM: SoC will enter low power mode before the ARM CPU executes WFI when improper low power
sequence is used
ERR011573 Core: Speculative accesses might be performed to memory unmapped in MPU.
ERR006223 Failure to resume from WAIT/STOP mode with power gating
ERR011377 FlexSPI: DLL lock status bit not accurate due to timing issue
ERR050606 LPSPI: TCR value does not get resampled when polling the register
ERR050607 LPSPI: TCR[FRAMSZ] can be ignored when TCR[TXMSK]=1b1
ERR050130 PIT: Temporary incorrect value reported in LMTR64H register in lifetimer mode
ERR050538 SOC: Potential boot failure on system reset if SJC_DISABLE fuse is blown
ERR050327 SWRESET on flexspi keyblob fetching state machine will impact software driver
Table 2. Revision History
Revision Changes
0 Initial revision
1 The following errata were added.
• ERR011573
• ERR050538
• ERR050606
• ERR050607
The following erratum was revised.
• ERR011377
NXP Semiconductors
i.MX RT1010CE
Chip Errata
Rev. 1
Chip Errata for i.MX RT1010
ERR050143: CCM: SoC will enter low power mode before the ARM CPU executes WFI
when improper low power sequence is used
Description:
When software tries to enter the low power mode with the following sequence, SoC enters the
low power mode before the ARM CPU executes the WFI instructions.
• Set CCM_CLPCR[1:0] to 2’b00
• ARM CPU enters WFI
• ARM CPU wakes up from an interrupt event, which is masked by GPC or not visible to GPC,
such as an interrupt from local timer.
• Set CCM_CLPCR[1:0] to 2’b01 or 2’b10
• ARM CPU executes WFI
Before the last step, SoC enters the WAIT mode if CCM_CLPCR[1:0] is set to 2’b01, or enters
the STOP mode if CCM_CLPCR[1:0] is set to 2’b10.
Workaround:
Software workaround
1) Trigger IRQ #41 (IOMUX), which is always pending by setting IOMUX_GPR1_GINT bit
2) Unmask IRQ #41 in GPC before setting the CCM low power mode
3) Mask IRQ #41 right after the CCM low power mode is set (set bit0-1 of CCM_CLPCR)
ERR011573: Core: Speculative accesses might be performed to memory unmapped in
MPU.
Description:
Arm errata 1013783-B
Cortex-M7 can perform speculative memory accesses to Normal memory for various reasons.
All other types of memory should never be subject to speculative accesses.
The memory attributes for a given address are defined by the settings of the MPU when it is
enabled. Regions that are not mapped in the MPU do not have any explicit attributes and
should not be subject to any speculative accesses.
Because of this erratum, Cortex-M7 can incorrectly perform speculative accesses to such
unmapped regions.
Conditions:
To trigger this erratum, the data cache must be enabled and the MPU must be enabled with
the default memory map disabled. That is:
• CCR.DC = 1; data cache is enabled.
• MPU_CTRL.ENABLE = 1; MPU is enabled.
• If MPU_CTRL.PRIVDEFNA = 1, then this erratum cannot occur from privileged mode.
• If MPU_CTRL.HFNMIENA = 1, then this erratum cannot occur from the NMI or HF handlers
or exception handlers when FAULTMASK = 1.
In these situations, a PLD instruction targeting an unmapped region might result in an incorrect
speculative access. The PLD instruction itself could be speculative because of branch
prediction. Even a literal data value that corresponds to a PLD encoding could theoretically
cause this issue. This makes it difficult to scan code to check if these conditions apply.
Chip Errata for i.MX RT1010, Rev. 1
2 NXP Semiconductors