MAX24405, M

AX24410

5 or 10 Output Any-Rate Clock Multipliers

General D es cription

The MAX24405 and MAX24410 are flexible, high-

performance clock multiplier/synthesizer ICs with two

independent APLLs. Each APLL performs any-to-any

frequency conversion. From any input clock frequency

9.72MHz to 750MHz these devices can produce

frequency-locked APLL output frequencies up to

750MHz and as many as 10 differential output clock

signals that are integer divisors of the APLL

frequencies. Output jitter is typically 0.35 to 0.5ps RMS

(12kHz to 20MHz) on all outputs and can be as low as

0.24ps RMS. Each device can configure itself from an

external EEPROM so that clock signals are available

immediately after power-up or reset.

Applications

Frequency Conversion and Synthesis Applications in a

Wide Variety of Equipment Types

Order ing Information

PART OUTPUTS PIN-PACKAGE

MAX24405EXG+

5 81-CSBGA (10mm)

MAX24410EXG+

10 81-CSBGA (10mm)

Features

♦ Input Clocks

♦ One Crystal or CMOS Input

♦ Three Differential or CMOS Inputs

♦ Differential to 750MHz, CMOS to 125MHz

♦ Clock Selection By Pin or Register Control

♦ Two APLLs Plus 5 or 10 Output Clocks

♦ APLLs Perform High Resolution Fractional-N

Clock Multiplication

♦ Any Output Frequency from <1Hz to 750MHz

♦ Each Output Has an Independent Divider

♦ Output Jitter 0.35 to 0.5ps RMS Typical on All

Outputs, Can Be As Low As 0.24ps RMS

♦ Outputs are CML or 2xCMOS, Can Interface to

LVDS, LVPECL, HSTL, SSTL and HCSL

♦ CMOS Output Voltage from 1.5V to 3.3V

♦ General Features

♦ Automatic Self-Configur at ion a t Pow er -Up

from External EEPROM Memory

♦ SPI™ Processor Interface

♦ 1.8V + 3.3V Operation (5V Tolerant)

♦ -40 to +85

°C Operating Temp. Range

Block Diagr am

RST_N

CS_N

SCLK

SDI

SDO

AC / GPIO1

TEST

IC1POS/NEG

IC2POS/NEG

OC1POS/NEG

DIV1

OC2POS/NEG

DIV2

OC3POS/NEG

DIV3

OC4POS/NEG

DIV4

OC5POS/NEG

DIV5

OC6POS/NEG

DIV6

OC7POS/NEG

DIV7

OC8POS/NEG

DIV8

OC9POS/NEG

DIV9

OC10POS/NEG

DIV10

IC3POS/NEG

APLL1

3.7-4.2GHz,

Sub-ps jitter,

Fractional-N

Processor SPI Interface

EEPROM SPI Interface

and HW Control and Status Pins

SS / GPIO2

GPIO3

GPIO4

INTREQ

XIN

XOUT

APLL2

3.7-4.2GHz,

Sub-ps jitter,

Fractional-N

JTAG

JTRST_N

JTMS

JTCLK

JTDI

JTDO

ECS_N

ESCLK

ESDI

ESDO

Short Form Data Sheet

June 2012

MAX24410 only

MAX24405, MAX2 4410

Short Form Data Sheet

Applicat ion Examples

Figure 1-1. Asynchronous Ethernet Clocks

Any combination of 25MHz,

125MHz, 156.25MHz and

related Ethernet frequencies

25MHz

Any combination of differential or

2x single-ended signal format

OC1P/N

OC2P/N

OC3P/N

OC4P/N

OC5P/N

OC6P/N

OC7P/N

OC8P/N

OC9P/N

OC10P/N

XIN

XOUT

Figure 1-2. Synchronous Ethernet and SDH/SONET Line Card

From dual

redundant

timing functions

OC1P/N

OC2P/N

OC3P/N

OC4P/N

OC5P/N

OC6P/N

OC7P/N

OC8P/N

OC9P/N

OC10P/N

IC1P/N

Synchronous Ethernet

Clocks: any combination

of 25M, 125M, 156.25M

and related frequencies

Any combination of differential or

2x single-ended signal format

19.44M,

25M, etc.

SDH/SONET Clocks:

Nx6.48MHz to 622.08MHz

IC2P/N