74ALVC16834A
18-bit registered driver with inverted register enable; 3-state
Rev. 2 — 21 November 2017 Product data sheet
1 General description
The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low
output enable (OE), active low latch enable (LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held
at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is
stored in the latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the state of the latch/
flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied
to V
CC
through a pull-up resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
2 Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low-power consumption
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Current drive ± 24 mA at V
CC
= 3.0 V
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
• Output drive capability 50 Ω transmission lines at 85°C
• Input diodes to accommodate strong drivers
• Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
Nexperia
74ALVC16834A
18-bit registered driver with inverted register enable; 3-state
74ALVC16834A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 2 — 21 November 2017
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3 Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74ALVC16834ADGG -40 °C to + 85 °C TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
4 Functional diagram
aaa-027713
OE
CP
LE
A1
Y1
D
LE
CP
to the 17 other channels
Figure 1. Logic diagram
aaa-027713
27
30
28
3
OE
CP
LE
Y1 A1
C3
EN1
G2
2C3
54
5
Y2 A2
52
6
Y3 A3
51
8
1 3D1Y4 A4
49
9
Y5 A5
48
10
Y6 A6
47
12
Y7 A7
45
13
Y8 A8
44
14
Y9 A9
43
15
Y10 A10
42
16
Y11 A11
41
17
Y12 A12
40
19
Y13 A13
38
20
Y14 A14
37
21
Y15 A15
36
23
Y16 A16
34
24
Y17 A17
33
26
Y18 A18
31
Figure 2. Logic symbol (IEEE/IEC)
002aac725
A1
V
CC
Figure 3. Typical input (data or control)