Revision 0.2
August 2003
K1S321611C
- 1 -
UtRAM
Preliminary
Document Title
2Mx16 bit Uni-Transistor Random Access Memory
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
0.1
0.2
Remark
Advanced
Preliminary
Preliminary
History
Initial Draft
Revised
- Deleted 60ns Speed Bin
Revised
- Corrected errorta ’48-TBGA’ under PIN DESCRIPTION to ’48-FBGA’
on page2
Draft Date
January 16, 2003
June 13, 2003
August 13, 2003
Revision 0.2
August 2003
K1S321611C
- 2 -
UtRAM
Preliminary
PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Speed
Power Dissipation
PKG Type
Standby
(ISB1, Max.)
Operating
(ICC2, Max.)
K1S321611C-I Industrial(-40~85°C) 2.7V~3.1V 70ns 100µA 35mA 48-FBGA-6.00x8.00
2M x 16 bit Uni-Transistor CMOS RAM
GENERAL DESCRIPTION
The K1S321611C is fabricated by SAMSUNG′s advanced
CMOS technology using one transistor memory cell. The device
supports Industrial temperature range and 48 ball Chip Scale
Package for user flexibility of system design. The device also
supports dual chip selection for user interface.
FEATURES
• Process Technology: CMOS
• Organization: 2M x16 bit
• Power Supply Voltage: 2.7V~3.1V
• Three State Outputs
• Compatible with Low Power SRAM
• Dual Chip selection support
• Package Type: 48-FBGA-6.00x8.00
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
1) Reserved for future use.
Name Function Name Function
CS1,CS2 Chip Select Inputs Vcc Power
OE Output Enable Input Vss Ground
WE Write Enable Input UB Upper Byte(I/O9~16)
A0~A20 Address Inputs LB Lower Byte(I/O1~8)
I/O1~I/O16 Data Inputs/Outputs NC
No Connection
1)
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O1~I/O8
Data
cont
Data
cont
Data
cont
I/O9~I/O16
Vcc
Vss
Precharge circuit.
Memory array
I/O Circuit
Column select
WE
OE
UB
CS1
LB
Control Logic
CS2
Row
Addresses
Column Addresses
PIN DESCRIPTION
48-FBGA: Top View(Ball Down)
LB OE A0 A1 A2 CS2
I/O9 UB A3 A4 CS1 I/O1
I/O10 I/O11 A5 A6 I/O2 I/O3
Vss I/O12 A17 A7 I/O4 Vcc
Vcc I/O13 NC A16 I/O5 Vss
I/O15 I/O14 A14 A15 I/O6 I/O7
I/O16 A19 A12 A13 WE I/O8
A18 A8 A9 A10 A11 A20
1 2 3 4 5 6
A
B
C
D
E
F
G
H