Si5381/82 Rev E Data Sheet

Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier with

Ultra-Low Noise

The Si5381/82 is an ultra high performance wireless jitter attenuator with multiple

DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) ap-

plications. The industry’s first multi-PLL wireless jitter attenuator device is capable of

replacing multiple discrete, high performance, VCXO-based jitter attenuators with a

fully integrated single chip solution. The featured multi-PLL architecture supports tim-

ing paths for Ethernet and CPRI (Common Public Radio Interface) clock cleaning ,

and generates any low-jitter, general-purpose clocks. The fixed frequency oscillator

provides frequency stability for free-run and holdover modes. This all-digital solution

provides superior performance that is highly immune to external board disturbances

such as power supply noise.

Applications:

• Wireless Infrastructure

• eCPRI RRH (Remote Radio Head)

• BBU (Baseband Unit)

• DU (Distribution Unit)

• Test and Measurement

KEY FEATURES

• Supports simultaneous Ethernet, CPRI and

general-purpose clocking in a single device

• Input frequency range:

• Differential: 8 kHz - 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range:

• CPRI: up to 2.94912 GHz

• Other differential: up to 735 MHz

• LVCMOS: up to 250 MHz

• Ultra-low RMS jitter:

• 72 fs typ (12 kHz–20 MHz)

• Phase noise of 122.88MHz carrier frequency:

• -118 dBc/Hz @ 100Hz offset

• ITU-T G.8262 compliant

DSPLL

IN1

IN2

IN3

IN0

OUT6

OUT5

OUT4

OUT0

OUT3

OUT2

OUT1

OUT0A

÷R

NVM

Control

Status

OUT9A

OUT9

OUT8

OUT7

÷R

÷P

DSPLL

IN_SEL

54 MHz

OSC

Any-Rate

PLLs

14.7456 GHz

PLL

Si5381

Si5382

C/SPI

Status Flags

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

1 Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 1

Table of Contents

1. Features List ...............................4

2. Ordering Guide ..............................5

3. Functional Description............................6

3.1 Frequency Configuration ..........................6

3.1.1 Si5381/82 CPRI Frequency Configuration ...................6

3.1.2 Si5381/82 Configuration for Wireless Clock Generation ...............7

3.2 DSPLL Loop Bandwidth ...........................8

3.3 Fastlock Feature .............................8

3.4 Modes of Operation ............................8

3.4.1 Initialization and Reset ..........................8

3.4.2 Freerun Mode .............................9

3.4.3 Lock Acquisition Mode ..........................9

3.4.4 Locked Mode .............................9

3.4.5 Holdover Mode ............................9

3.4.6 VCO Freeze Mode ...........................10

3.5 External Reference (XA/XB) .........................10

3.6 Inputs (IN0, IN1, IN2, IN3) ..........................11

3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3) ...................11

3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3) ..................12

3.6.3 Hitless Input Switching ..........................12

3.6.4 Ramped Input Switching .........................12

3.6.5 Glitchless Input Switching .........................12

3.7 Fault Monitoring .............................13

3.7.1 Input LOS Detection...........................13

3.7.2 Reference Clock LOS Detection.......................13

3.7.3 OOF Detection ............................14

3.7.4 LOL Detection.............................15

3.7.5 Interrupt Pin (INTRb) ..........................17

3.8 Outputs ................................17

3.8.1 Output Crosspoint ...........................18

3.8.2 Output Signal Format ..........................18

3.8.3 Output Terminations ...........................19

3.8.4 Programmable Common Mode Voltage For Differential Outputs ............19

3.8.5 LVCMOS Output Impedance and Drive Strength Selection ..............20

3.8.6 LVCMOS Output Signal Swing .......................20

3.8.7 LVCMOS Output Polarity .........................20

3.8.8 Output Enable/Disable ..........................20

3.8.9 Output Disable During LOL ........................20

3.8.10 Output Disable During Reference LOS ....................20

3.8.11 Output Driver State When Disabled .....................20

3.8.12 Synchronous Output Disable Feature ....................21

3.8.13 Static Output Skew Control ........................21

3.8.14 Dynamic Output Skew Control .......................21

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

2 Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 3, 2021 2