FPGA-PB-02001 Workaround for Lattice ECP5 (LFE5UM)
Known Issue with SerDes Interface Connections Due to
Unstable Reset Soft Logic
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Product
Bulletin
Workaround for Lattice ECP5 (LFE5UM) Known Issue with
Ser Des Interface Connections Due to Unstable Reset Soft Logic
Product Affected: All ECP5 and ECP5-5G with SerDes(LFE5UM and LFE5UM-5G) devices are
covered by this Product Bulletin.
Customers Affected: Only customers using SerDes/PCS-based designs. It potentially affects
several applications such as PCIe, g8B10B, and SGMII. The workaround is organized on single
channel basis, contact your local Lattice representative for other use cases.
Background: The Lattice Semiconductor ECP5 FPGA devices may contain SerDes. These parts
with SerDes can be implemented through Clarity Designer by using the PCS module. The PCS
module comes with a custom soft logic reset, which helps users automatically reset the receiver
portion of the PCS.
Observation: Lattice found that in specific situations, the original soft logic reset is not as stable
as intended. Some unexpected behaviors include the Receiver CDR failing to lock and the
receiver data being unstable. This document provides the workaround procedure to resolve these
issues.
Detailed Workaround Description:
This workaround is organized on a single channel basis, contact your local Lattice representative
for other use cases.
Lattice developed a workaround procedure that implements ‘extended Reset Soft Logic = extRSL’
to bring-up the SerDes/PCS at a stable state. The workaround is to remove the current receiver
reset signals from the current RSL and add a new module that will drive the receiver reset signals
instead.
The new source code contains the necessary functions for a detailed signal monitoring and
controlled reset scenario. It is the single point of control for all the receiver resets in the PCS
portion of the design. The transmitter reset signals will still be driven by the original RSL.
It supports the controlled reset sequencing for the different blocks, such as:
 Default power-up situation: Enhanced power-up reset sequence for higher stability. (Refer
to Figure 4)
 Receiver Clock Data Recovery block is locked and stable. (Refer to Figure 5)
 PCS block is locked and stable. (Refer to Figure 6)
If these settings are detected, the design releases all resets, resulting to a stable design.
If any of the cases below occurs, the reset scenario starts from the beginning (Refer to Figure 7):
 Code violation error the FSM restarts the PCS again.
 RX loss of signal or the TX_PLL will lose its lock.
For the cascaded resets of different functions in the SerDes, the user can select default reset
periods as minimum step width. These variables are counter timers for specific portions of the
reset sequence. Tplol value is the amount of time transmit PLL to lock, tcdr is the amount of time
receiver CDR has to lock and tviol is the amount of time to wait for code violation and disparity
June 2021
FPGA-PB-02001
FPGA-PB-02001 Workaround for Lattice ECP5 (LFE5UM)
Known Issue with SerDes Interface Connections Due to
Unstable Reset Soft Logic
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error before concluding the PCS is correct. Note that depending on your design, these values
might have to be adjusted. For example, if the reference clock used for the Transmit PLL is more
jittery, the Tplol might have to be adjusted to a higher value. (Refer to Figure 8)
Note:
The extended Reset Soft Logic is instantiated into the PCS block generated from Clarity Designer.
Keep in mind that once extRSL is instantiated to the PCS block, every new generation in Clarity
overrides the user’s modification so make sure to save your work beforehand. This
implementation also assumes that the setting Disable RSL is not active.