Key Sheet
AD7193
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Highlights of the AD7193 Low Noise, 24-Bit Sigma-Delta ADC
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
F
igure 1. Functional Block Diagram
GENERAL DESCRIPTION
This key sheet
1
provides users with an overview of the AD7193.
Key attributes of the part include the following:
• Designed for the measurement of wide dynamic range, low
frequency signals, such as those in pressure transducers, strain
gauge transducers, flow measurement, chromatography
,
a
nd data acquisition system
s.
• L
ow power, flexible, high performance, ultralow noise, 24-bit
Sigma-Delta (Σ-Δ) ADC suitable for converting low inpu
t
b
andwidth analog signals with a fully flexible output data
rate (ODR) between 4.7 SPS to 4.8 kSPS.
• An on-chip low noise gain stage allows signals of small
a
mplitude to interface directly to the ADC.
• Combines four differential or eight pseudo differential
input channels with low power consumption.
• With an ODR of 4.7 SPS and a gain of 128, the AD7193
boasts an rms noise of 11 nV.
• User friendly, with the part being fully configurable over a
4-wire serial interface.
• Available in 28-lead TSSOP and 32-lead LFCSP packages.
FEATURES AND BENEFITS
The AD7193 offers the following features and benefits:
• Mains power supply interference
• Simultaneous 50 Hz and 60 Hz rejection at 50 SPS ODR
• Programmable gains of 1, 8, 16, 32, 64, and 128
• Automatic channel sequencer
• On-chip temperature sensor
• Internal and system calibration on chip
• Option of 4.92 MHz internal clock or external crystal
• Digital filter options include using a Sinc
4
or Sinc
3
filter,
chop enabled or disabled, fast settling, and zero latency
• Ultralow noise performance across the ODR range
• Fully SPI, QSPI™, MICROWIRE®, and DSP compatible
• SPI configuration control
• 3-wire serial digital interface (Schmitt trigger on SCLK)
1
This document provides users with an overview of the AD7193; it is not a notice of performance or intent. Refer to the AD7193 data sheet for performance and more
specific information about this product.
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
DV
DD
DGND REFIN1(+) REFIN1(–)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AGND
AD7193
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
CLOCK
CIRCUITRY
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
AV
DD
AGND
AIN5
AIN6
AIN7
AIN8
Σ-Δ
ADC
PGA
MUX
11262-001
AD7193 Key Sheet
Rev. 0 | Page 2 of 6
KEY CHARACTERISTICS
FUNDAMENTAL SPECIFICATIONS
Table 1.
Parameter Min Typ Max Unit
ADC Type Σ- Δ ADC
Number of Input Channels Four differential or eight pseudo differential input channels
Resolution 24 24 Bits
Output Data Rate 4.7 4800 SPS
Differential ADC Input Range −V
REF
/gain +V
REF
/gain V
AV
DD
with Respect to AGND 3 5.25 V
AI
DD
Current
With Gain = 1, Buffer Off 0.85 1 mA
With Gain = 16 to 128, Buffer On 4.3 5.3 mA
DI
DD
Current (DV
DD
= 3 V)
0.35
0.4
mA
Offset Error ±150/gain µV/gain
Offset Error Drift vs. Temperature
1
±150/gain nV/°C/gain
Full-Scale Error ±10 µV
Gain Drift vs. Temperature ±1 ppm/°C
Integral Nonlinearity (INL)
2
−10 ±2 +10 ppm of FSR
Power Supply Rejection 90 dB
Operating Temperature Range −40 +105 °C
1
Gain = 1 to 16; chop disabled.
2
AV
DD
= 5 V, Gain = 1.
NOISE
Sinc
4
Chop Disabled Filter Setting
Table 2. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word
(Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
RMS Noise (nV)
G = 1 G = 8 G = 16 G = 32 G = 64 G = 128
1023 4.7 852.5 340 53 34 18 12 11
96 50 80 950 150 80 50 37 31
80 60 66.7 1000 160 90 54 40 35
1 4800 0.83 26,000 3400 1700 910 530 380
Fast Settling Filter Setting
Table 3. RMS Noise (nV) vs. Gain and Output Data Rate
Filter Word
(Decimal)
Output Data
Rate (Hz)
Settling
Time (ms)
RMS Noise (nV)
G = 1 G = 8 G = 16 G = 32 G = 64 G = 128
96
2.63
380
380
87
52
33
15
11
30 8.4 118.75 620 140 71 43 30 21
6 42.10 23.75 1300 270 150 82 56 47
5 50.53 19.79 1500 280 160 88 61 50
2 126.32 7.92 2300 380 210 130 88 77
1 252.63 3.96 3400 520 290 180 130 110