TL/F/9500
54F/74F219 64-Bit Random Access Memory with TRI-STATE Outputs
November 1994
54F/74F219
64-Bit Random Access Memory with TRI-STATE
É
Outputs
General Description
The ’F219 is a high-speed 64-bit RAM organized as a
16-word by 4-bit array. Address inputs are buffered to mini-
mize loading and are fully decoded on-chip. The outputs are
TRI-STATE and are in the high-impedance state whenever
the Chip Select (CS
) input is HIGH. The outputs are active
only in the Read mode. This device is similar to the ’F189
but features non-inverting, rather than inverting, data out-
puts.
Features
Y
TRI-STATE outputs for data bus applications
Y
Buffered inputs minimize loading
Y
Address decoding on-chip
Y
Diode clamped inputs minimize ringing
Y
Available in SOIC (300 mil only)
Commercial Military
Package
Package Description
Number
74F219PC N16E 16-Lead (0.300
×
Wide) Molded Dual-In-Line
54F219DL (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F219SC (Note 1) M16B 16-Lead (0.300
×
Wide) Molded Small Outline, JEDEC
74F219SJ (Note 1) M16D 16-Lead (0.300
×
Wide) Molded Small Outline, EIAJ
54F219FL (Note 2) W16A 16-Lead Cerpack
54F219LL (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13
×
reel. Use suffix
e
SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
e
DLQB, FLQB and LLQB.
Logic Symbol
TL/F/9500–1
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9500–2
Pin Assignment
for LCC
TL/F/9500–3
TRI-STATE
É
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
A
0
–A
3
Address Inputs 1.0/1.0 20 mA/
b
0.6 mA
CS
Chip Select Input (Active LOW) 1.0/2.0 20 mA/
b
1.2 mA
WE
Write Enable Input (Active LOW) 1.0/1.0 20 mA/
b
0.6 mA
D
0
–D
3
Data Inputs 1.0/1.0 20 mA/
b
0.6 mA
O
0
–O
3
TRI-STATE Data Outputs 150/40 (33.3)
b
3 mA/24 mA (20 mA)
Function Table
Inputs
Operation Condition of Outputs
CS WE
L L Write High Impedance
L H Read True Stored Data
H X Inhibit High Impedance
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Block Diagram
TL/F/9500–4
2