CHA3395-QDG
Ref. : DSCHA3395-QDG1306 - 2 Nov 21
1/16
Specifications subject to change without notice
United Monolithic Semiconductors S.A.S.
Bât. Charmille - Parc Mosaic - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-rf.com
21-30GHz Medium Power Amplifier
GaAs Monolithic Microwave IC in SMD leadless package
Description
The CHA3395-QDG is a 3 stage monolithic
Medium Power Amplifier, which produces
24dB gain for 20dBm output power.
It is designed for a wide range of
communication and sensor systems.
The circuit is manufactured with a pHEMT
process, 0.25µm gate length, via holes
through the substrate, air bridges and
electron beam gate lithography.
It is supplied in RoHS compliant SMD
package.
Main Features
Output Power & PAE versus Frequency
■ Broadband performances: 21-30GHz
■ 20dBm Pout at 1dB compression
■ 24dB gain
■ 32dBm OTOI
■ DC bias: Vd= 4.0V, Id= 180mA
■ 24L-QFN4x4 (QDG)
■ MSL1
Main Electrical Characteristics
Tamb.= +25°C
Symbol
Parameter
Min
Typ
Max
Unit
Freq
Frequency range
21
30
GHz
Gain
Linear Gain
24
dB
P-1dB
Output Power @1dB comp.
20
dBm
OTOI
3
rd
order Intercept point
32
dBm
10
12
14
16
18
20
22
24
26
28
30
19 20 21 22 23 24 25 26 27 28 29 30
Output Power (dBm), PAE (%)
Frequency (GHz)
Psat
P-1dB
PAE sat
UMS
A3667A
YYWWG
UMS
A3667A
YYWWG
UMS
A3688A
YYWWG
UMS
A3667A
YYWWG
UMS
A3667A
YYWWG
UMS
A3688A
YYWWG
UMS
A3395
YYWW
CHA3395-QDG
21-30GHz Medium Power Amplifier
Ref. : DSCHA3395-QDG1306 - 2 Nov 21
2/16
Specifications subject to change without notice
Bât. Charmille - Parc Mosaic - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France
Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-rf.com
Electrical Characteristics
Tamb.= +25°C, Vd = +4.0V
Symbol
Parameter
Min
Typ
Max
Unit
Freq
Frequency range
21
30
GHz
Gain
Linear Gain 21-29.5 GHz
Linear Gain 30 GHz
24
21
dB
ΔG
Gain variation in temperature
0.023
dB/°C
G
CTRL
Gain control range
15
dB
OTOI
3
rd
order Intercept point
32
dBm
P
-1dB
Output power @ 1dB compression
20
dBm
Psat
Saturated Output Power
22
dBm
RLin
Input Return Loss
12
dB
RLout
Output Return Loss
20
dB
NF
Noise figure
4.5
dB
Id
Quiescent Drain current
180
mA
Vg
Gate voltage
-0.4
V
These values are representative of onboard measurements as defined on the drawing in
paragraph "Evaluation board".
“Power ON” sequence
1. Ground the device
2. Bias MPA gate voltage at Vg low enough (Typically: Vg -1V)
3. Apply Vds bias voltage (Typically: Vd = 4V)
4. Increase slowly Vgs up to quiescent bias drain current Idq
5. Apply RF signal
“Power OFF” sequence
1. Turn off RF signal
2. Bias MPA gate voltage at Vg low enough (Typically: Vg -1V)
3. Turn Vds bias voltage to 0V
4. Turn Vgs bias voltage to 0V