a
ABOUT ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 SILICON ANOMALIES
These anomalies represent the currently known differences between revisions of the SHARC+®ADSP-21591/21593/21594/ADSP-SC591/
SC592/SC594 product(s) and the functionality specified in the ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 data sheet(s) and
the Hardware Reference book(s).
SILICON REVISIONS
A silicon revision number with the form "-x.x" is branded on all parts. The REVID bits <31:28> of the TAPC0_IDCODE register can be
used to differentiate the revisions as shown below.
Silicon REVISION TAPC0_IDCODE.REVID
0.0 b#0000
ANOMALY LIST REVISION HISTORY
The following revision history lists the anomaly list revisions and major changes for each anomaly list revision.
Date Anomaly List Revision Data Sheet Revision Additions and Changes
08/25/2021 D Rev0/PrE Added Anomaly 20000118
08/12/2021 C Rev0/PrE Updated Anomalies 20000115, 20000117
05/21/2021 B PrD Added Anomalies 20000110, 20000113, 20000114, 20000115, 20000117
10/15/2020 A PrA Initial Version
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
www.analog.comTechnical Support
Document Feedback
DSP with ARM Cortex-A5
SHARC+ Dual-Core
Silicon Anomaly List
SHARC+ and SHARC are registered trademarks of Analog Devices, Inc.
NR004832D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 ©2021 Analog Devices, Inc. All rights reserved.
SUMMARY OF SILICON ANOMALIES
The following table provides a summary of ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594 anomalies and the applicable silicon
revision(s) for each anomaly.
No. ID Description Rev
0.0
1 20000002 Data Forwarding from Rn/Sn to DAG Register May Fail in Presence of Stalls x
2 20000003 Transactions on SPU and SMPU MMR Regions May Cause Errors x
3 20000031 GP Timer Generates First Interrupt/Trigger One Edge Late in EXTCLK Mode x
4 20000062 Writes to the SPI_SLVSEL Register Do Not Take Effect x
5 20000069 PCSTK and MODE1STK Loads Do Not Occur If Next Instruction Is L2 or L3 Access x
6 20000072 Floating-Point Computes Targeting F0 Register Can Cause Pipeline Stalls x
7 20000096 Type 18a USTAT Instructions Fail When Following Specific Code Sequence x
8 20000110 Secure Image Authentication gets bypassed during autodetection (default mode) for Master boot modes on
power on reset, when the processor is locked
x
9 20000113 UART3 slave boot not functional with autobaud detection enable in UART Slave boot command x
10 20000114 Circular Buffering in FIR Accelerator may not work properly in "burst access of length 16 words" mode x
11 20000115 On LPC ADSP-SC59x processors, SYS_FAULT/SYS_FAULT# signal are active out of reset x
12 20000117 DMC PHY Calibration issue x
13 20000118 FIR accelerator may produce wrong output for tap length greater than 1024 (multi-iteration mode) with
prefetch buffer feature enabled.
x
Key: x = anomaly exists in revision
. = Not applicable
ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594
NR004832D | Page 2 of 10 | August 2021
Silicon Anomaly List