1. Electrical Specification
1-1 Test condition
Varistor voltage
In = 1 mA DC
Leakage current
Vdc = 15 V DC
Maximum clamping voltage
Ic = 1 A
Rated peak single pulse transient current
8 / 20 waveform, +/- each 1 time induce
Capacitance
10/1000 waveform
Insulation resistance after reflow soldering
f = 1MHz, Vrms = 0.5 V
Reflow soldering condition
Soldering paste : Tamura (Japan) RMA-20-21L
Stencil : SUS, 120 thickness
Pad size : 0.8 (Width) x 0.9 (Length)
0.8 (Distance between pads)
Soldering profile : 260±5 , 5 sec.
1-2 Electrical specification
Maximum allowable continuous DC voltage
15
V
trigger voltage / Varistor voltage / breakdown voltage
110-125
V
Maximum clamping voltage
200
V
Maximum
Rated peak single pulse transient current
1
A
Maximum
Nonlinearity coefficient
12
Leakage current at continuous DC voltage
0.1
Response time
0.5
ns
Varistor voltage temperature coefficient
0.05
%/
Capacitance measured at 1MHz
2.5
pF
Typical
Capacitance tolerance
±30
%
Insulation resistance after reflow soldering on PCB
10
M
Operating ambient temperature
-55 to +125
Storage temperature
-55 to +125
PESD1563U250
Rev : www.leiditech.com
01.06.2018
1/5
1-3 Reliability testing procedures
Reliability
parameter
Test
Test requirement
Pulse current
capability
Imax
8/20
IEC 1051-1, Test 4.5.
10 pulses in the same direction at 2
pulses per minute at maximum peak
current
dVn/Vn 10%
no visible damage
Electrostatic
discharge
capability
ESD
C=150 pF,
R=330
IEC 1000-4-2
Each 10 times in positive/negative
direction in 10 sec at 8KV contact
discharge (Level 4)
dVn/Vn 10%
no visible damage
Environmenta
l reliability
Thermal shock
IEC 68-2-14
Condition for 1 cycle
Step 1 : Min. 40, 30±3 min.
Step 2 : Max. +125, 30±3 min.
Number of cycles: 30 times
dVn/Vn 5%
no visible damage
Low temperature
IEC 68-2-1
Place the chip at -40±5 for 1000±
12hrs. Remove and place for 24±2hrs at
room temp. condition, then measure
dVn/Vn 5%
no visible damage
High temperature
IEC 68-2-2
Place the chip at 125±5 for 1000±
24hrs. Remove and place for 24±2hrs at
room temp. condition, then measure
dVn/Vn 5%
no visible damage
Heat resistance
IEC 68-2-3
Apply the rated voltage for 1000±48hrs at
85±3. Remove and place for 24±2hrs
at room temp. condition, then measure
dVn/Vn 5%
no visible damage
Humidity
resistance
IEC 68-2-30
Place the chip at 40±2 and 90 to 95%
humidity for 1000±24hrs. Remove and
place for 24±2hrs at room temp.
condition, then measure
dVn/Vn 10%
no visible damage
Pressure cooker
test
dVn/Vn 10%
no visible damage
PESD1563U250
Rev : www.leiditech.com
01.06.2018
2/5