This document describes ho w to design a platform with a common footprint for the MPC750,
MPC755, MPC7400, and MPC7410; that is, it is intended to help design a single board
compatible with all of these de vices. Although this document contains rele v ant information, it
is not intended to be a complete migration guide for moving from G3- to G4-class systems.
As a general note, refer to the appropriate hardware specifications and user’s manual for the
specific device under consideration.
For this document, the following system definition is assumed for the MPC750, MPC755,
MPC7400 and MPC7410:
• 64-bit data bus mode
• No data retry
• Bus operates in 60x mode
Note that all the CPUs can run in 60x bus, and the MPC7400 and MPC7410 have the ability
to run in an enhanced mode MPX.
Advance Information
AN1812/D
Rev. 1, 12/2001
Common Footprint for the
MPC750, MPC755,
MPC7400, and MPC7410
CPD Applications
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Freescale Semiconductor, Inc.
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Common Footprint for the MPC750, MPC755, MPC7400, and MPC7410
Main Pin Difference
1.1 Main Pin Difference
This section includes Table 1 which lists the main differences between the MPC750, MPC755, MPC7400
and MPC7410 and the configuration pins. The MPX b us column pro vides information for designers to tak e
advantage of the MPX bus mode for future board revisions.
Table 1. Main Pin Difference and Configuration Pins
Pin # Type MPC750 MPC755
MPC7400/
MPC7410
60x Bus
MPC7400/
MPC7410
MPX Bus
Comment
B3 I/O No Connect No Connect SHD[0] SHD[0] Pull-up (in multi CPU system,
connect together)
1
B4 I/O No Connect No Connect SHD[1] SHD[1] Pull-up (in multi CPU system,
connect together)
1
B5 Output No Connect No Connect No Function HIT Pull-up to OVDD
1
K9 Output No Connect No Connect No Function DRDY
K19 Output No Connect No Connect L2A17 L2A17 Connect to L2 SRAM. A pull-up
to L2VODD should be used if
MPC750/MPC755 1Mbyte
compatibility is required when
using 2Mbytes of SRAM.
W19 Output No Connect No Connect L2A18 L2A18 Reserved for future expansion
A4 Input PLL_CFG[0] PLL_CFG[0] PLL_CFG[0] PLL_CFG[0] See hardware specification
document. Should put in a pull
up/down pair for each to allow
any configuration.
A5 Input PLL_CFG[1] PLL_CFG[1] PLL_CFG[1] PLL_CFG[1]
A6 Input PLL_CFG[2] PLL_CFG[2] PLL_CFG[2] PLL_CFG[2]
A7 Input PLL_CFG[3] PLL_CFG[3] PLL_CFG[3] PLL_CFG[3]
F9 Input LSSD_MODE
LSSD_MODE LSSD_MODE LSSD_MODE Pull-up to OVDD
F7 Input L2_TSTCLK L2_TSTCLK L2_TSTCLK L2_TSTCLK
F8 Input L1_TSTCLK L1_TSTCLK L1_TSTCLK L1_TSTCLK
K11 Input No Connect No Connect CHK CHK
K13 V OLDET V OLDET L2O VDD[13] L2O VDD[13] Must be connected to L2O VDD
L7 I/O or
Output
ABB
ABB ABB ABB Pull-up to OVDD
1
C2 I/O or
Output
CI CI CI CI
C3 I/O or
Output
WT WT WT WT
K5 I/O or
Output
DBB DBB DBB DBB
D1 Input DBWO DBWO DBWO DTI[0]
2
H6 Input DRTRY DRTRY No Function DTI[1]
2
Connect to HRESET for no
Data retry mode in 60x bus.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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