MCM6946•SCM6946
1
MOTOROLA FAST SRAM
512K x 8 Bit Static Random
Access Memory
The MCM6946/SCM6946 is a 4,194,304–bit static random access memory or-
ganized as 524,288 words of 8 bits. Static design eliminates the need for external
clocks or timing strobes.
The MCM6946/SCM6946 is equipped with chip enable (E
) and output enable
(G
) pins, allowing for greater system flexibility and eliminating bus contention
problems. Either input, when high, will force the outputs into high impedance.
The MCM6946 is available in a 400 mil, 36–lead surface–mount SOJ package.
• Single 3.3 V – 5%, + 10% Power Supply
• Fast Access Time: 8/10/12/15 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Three–State Outputs
• Power Operation: 195/185/180/175 mA Maximum, Active AC
• Available in TSOP or SOJ Packages
BLOCK DIAGRAM
G
AAAAAAAAA
MEMORY MATRIX
ROW
DECODER
INPUT
DATA
CONTROL
A
A
A
A
A
A
A
A
DQ
DQ
E
W
A
A
COLUMN I/O
COLUMN DECODER
DQ
DQ
Order this document
by MCM6946/D
SEMICONDUCTOR TECHNICAL DATA
YJ PACKAGE
400 MIL SOJ
CASE 893–02
MCM6946
SCM6946
A0 – A18 Address Inputs. . . . . . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . .
DQ Data Input/Output. . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . .
V
DD
+ 3.3 V Power Supply. . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . .
PIN NAMES
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
REV 8
1/29/99
Motorola, Inc. 1999
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc
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SCM6946•MCM6946
2
MOTOROLA FAST SRAM
PIN ASSIGNMENTS
5
4
3
2
1
10
9
8
7
6
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
19
27
28
32
31
30
29
36
35
34
33A
A
A
A
E
A
V
SS
V
DD
DQ
DQ
DQ
DQ
A
A
W
A
A
A
V
DD
DQ
DQ
A
A
A
A
A
NC
V
SS
A
A
A
G
DQ
DQ
NC
A
5
4
3
2
1
10
9
8
7
6
11
36
37
38
39
40
41
42
35
43
44
34
A
A
A
NC
NC
E
A
A
V
DD
DQ
DQ
A
A
NC
NC
NC
DQ
DQ
G
V
SS
A
A
25
26
27
28
29
30
31
24
32
33
23
12
13
14
15
16
17
18
19
20
21
22
A
A
DQ
DQ
V
DD
NC
NC
A
NC
A
AA
W
DQ
DQ
V
SS
A
A
A
NC
NC
A
400 MIL SOJ TSOP TYPE II
TRUTH TABLE
(X = Don’t Care)
E G W Mode I/O Pin Cycle Current
H X X Not Selected High–Z — I
SB1
, I
SB2
L H H Output Disabled High–Z — I
DDA
L L H Read D
out
Read I
DDA
L X L Write High–Z Write I
DDA
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage Relative to V
SS
V
DD
– 0.5 to 5.0 V
Voltage Relative to V
SS
for Any Pin
Except V
DD
V
in
, V
out
– 0.5 to V
DD
+ 0.5 V
Output Current (per I/O) I
out
± 20
mA
Power Dissipation P
D
1.0 W
Temperature Under Bias T
bias
– 10 to 85 °C
Operating Temperature T
A
0 to 70 °C
Storage Temperature — Plastic T
stg
– 55 to 150 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could af fect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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