High-speed, Loadable 16-bit Binary Counter

Introduction

The AT600 0 Series field progr ammable

gate array (FPGA) lets the designer

implement a fast synchronous, loadable

16-bit binary counter that operates at

70 MHz on and off chip under the worst

commercial operating conditions. The

use of prescaled logic to generate the

carry-enable signals for each coun t bit

allows faster operation than traditional

carry-enable generation methods. The

16-bit counter is very compact, yet the

inputs and outputs are readily

accessible.

Description

Figure 1 sh ows a block di agram repre-

senta tion of th e coun ter archite ctur e and

I/O. CLK is the clock signal, RST is the

reset s ignal, and L OAD is the load data

signal. CE is the count enable signal.

CLK is a positive, edge-triggered syn-

chronous signal, RST is an active low,

asynchronous signal, and LOAD is an

active low, synchronous signal. Pins D

through D

are the load data inputs,

pins Q

through Q

are the count bits.

Pin C

is the carry in, C

is the carry out.

Toggle fl ip-flops are use d as the register

elements for each bit of the counter.

They toggle on the rising edge of CLK

when their RST, CE, and T inputs pins

are high and the LOAD pin is low.

Figure 1. Architecture and I/O of 16-bit Counter

Field

Programmable

Gate Array

Application

Note

Rev. 0463C–09/99

FPGA

Initial po wer-up of the AT6000 de vice r esets all the regis-

ters so the counter begins counting on the first rising edge

of CLK if C

RST, and CE are set high and LOAD is set low.

The circuit c oun ts by allowi ng ea ch reg ister ele men t to tog-

gle in succession on the rising edge of CLK if the Q outputs

of all prior elements are asserted.

Asserting RST at any time inhibits counting, but also resets

the registers to low values.

Figure 2 sho ws the imp lemen tation of a r egist er element i n

the 16-bit counter logic architecture. The Q output of this

circuit will toggle if T and CE are high and LOAD is low on

the rising edge of CLK. If CE and LOAD are low, then Q will

not change, regardless of T. If CE is high and LOAD is low,

then Q will remain the same if T is low upon the rising edge

of CLK.

To loa d a value int o the coun ter, LOAD is set hi gh and CE

is set low before the rising edge of CLK. The value is

latched into the register elements on the rising edge of

CLK.

CE should then be held low until after the next rising edge

of CLK to allow the carry-enable logic time to recalculate

the T inputs for each register element. The carry-enable

logic is the chain of two-input AND gates that generates the

T signal inputs.

Figure 2. Schematic of 16-bit Counter Register Element

If LOAD is asserted for on e clock cycl e and CE is low for

two clock cycles, the data at D

0-15

is loaded into the regis-

ters on the first clock cycle, and the counting continues

from the newly loaded value on the second cycle

(Figure 3).

During the LOAD c ycle, when the data at D

0-15

is cl ocked

into the coun ter, the carry-e nable logic must have time to

generate and propa gate the results to ev ery bit. Since an

arbitrary number at D

0-15

can cause a carry-enable signal to

propagate along the entire length of the carry-enable chain,

the cr itica l path du ring a L OAD op erati on has th e poten tial

to pass thr oug h 14 AN D-g ate (AN2) stag es befor e en terin g

the last register element. By hold ing the CE signal low an

extra clock cycle to inhibit the counting operation (as shown

in Figure 3), the carry-enable logic has additional time to

propagate the correct values to each bit.

During normal operation Q

, the least-significant bit of the

counter, is also a fast carry-enable signal. As shown in Fig-

ure 4, the CE inputs of each register element ahead of the

first bit are ti ed to the Q

. All bits greater than Q

must wait

for Q

to switch from low to high before they can change on

the rising edge of CLK. As the more significant bits change,

their values trickle forward through the two-input AND

gates that form the carry-enable logic to the T inputs of suc-

ceed ing regi ster el ements . Distri buting Q

in this manner

allows an extra clock cycle for the chain of two-input AND

gate s to calcul ate the ca rry-e nable sig nal for th e T input of

each register element.

The exact layout of the fast car ry-enable logic for the first

severa l bits of the 16-bit counter is shown in Figure 5. By

replicating and concatenating the circuitry surrounded by

the dotted box, the entire counter function is realized. The

AN2 gates feed two-input XOR gates, (XO2). The FDMUX

macro provides a two-to-one multipl exer feeding the input

of a D-type flip-flop in a single cel l. The MUX macro is a

one-cell two-to-one multiplexer.

The performance and utilization statistics are given in

Table 1 . Both im plementatio ns are available i n schematic

and layout form.