Modeling Device Power Consumption

Introduction

The following provides a simple method

for modeling the active and static power

consumption of a AT6005 design.

Active Power

Consumption

Active power consumption is a function

of the distribution of resources in a

design and the numbe r of nets switch ing

each second. The distribution of

resources is calculated by counting the

instances in the design database. The

Integrated Development System (IDS)

reports this information in the list files

generated by programs like placement,

routing and bit stream g eneration. T he

switching of some nets, like clock signals

and flip-flop outputs, is determined by

clock frequency and can be tabulated

exactly. The switching of other nets,

especiall y combinatorial lo gic, is input-

depend ent and no t solely determ ined by

the clock. As a result, the activity of

these nodes can only be estimated.

Combinatorial signals are typically half

as active as the clock. Test vectors rep-

resentative of actual design operation

can give a more accurate calculation.

ViewLogic’s “activity” command calcu-

lates the number of active nodes in a

design during logic simulation.

The equa tion for activ e power co nsump-

tion is as follows:

POWER = Freq uenc y

× (Aa × Ka × Na +

× Kb × Nb + Al × Kl × Nl +

× Kx × Nx + Ac × Kc × Nc +

× Ng + Ai × Ki × Ni + Ao ×

Ko × No) × V

The N coefficients represent the design

resources reported by the IDS:

Na number o f A -t ype ne ts us ed ( ind i-

vidual cell function is not

important)

Nb number o f B -t ype ne ts us ed ( ind i-

vidual cell function is not

important)

Nl number of local-bus type nets

used

Nx number of express-bus type nets

used

Nc number of clock columns used

Ng 1 if global clock is used

Ni number of I/O inputs

No number of I/O outputs with no

output load used

The A coefficients represent the esti-

mated activity of combinatorial logic.

The K coefficients represent the weight-

ing factor of each component:

Ka = 2 µA/MHz Kb = 2 µA/MHz

Kl = 4 µA/MHz Kx = 3 µA/MHz

Kc = 100 µA/MHz Kg = 200 µA/MHz

Ki = 4 µA/MHz Ko = 60 µA/MHz

The am ount of activ ity pos sible is base d

on the number of each cell type used.

The AT6005 has the following available:

Na = 3136 Nb = 3136

Nl = 1568 Ne = 1568

Nc = 56 Ng = 1

Ki = 64 (84-pin) or 108 (132-pin)

Ko = 64 (84-pin) or 108 (132-pin)

If every n ode wer e activ e at 10 M H z, th e

devi ce would use a bout 293 m A of cur-

rent (1466 mW).

Field

Programmable

Gate Array

Application

Note

Rev. 0477C–09/99

FPGA

A more typical ex amp le woul d be:

Na = 2000 Ab = 2000

Al = 1200 Ae = 700

Ac = 27 Ag = 1

Ki = 54 Ko = 54

Yielding an active power consumption of:

POWER = 2000

× 0.5 × 2 + 2000 × 0.5 × 2 + 1200 × 0.5 × 4

+ 300

× 0.5 × 3 + 27 × 1 × 100 + 1 × 1 × 200 + 54

× 0.5 × 4 + 54 × 0.5 × 60

= 11.5 mA/MHz

Or, 115 mA at 10 MHz (575 mW at 10 MHz).

Quiescent Power Consumption

The AT6005 is a CMOS device. Once programmed, the

SRAM used to st ore the configuratio n requires no static

power. The programmable interconnect points use comple-

mentary CMOS pass gates; this insures that all signals

eventually reach V

or GND and dissipate no static power.

There are no passive pull-ups on any internal nodes.

Unused nets and buses are tied to V

and GND, and

dissip ate no p ower. Tri-states wit hout active driver s dissi-

pate some stati c power, but thi s is easily av oid ed.

Static power dissipation, measured after power-up in

modes 1, 2, 3, or 6, but before programming, is 2 mA. After

power-up, the devic e is prog rammed as a large arr ay of

registers with no inputs connected. Modes 4 and 5 gener-

ate a clock output signal. The power dissipation of modes

4 and 5 is 2 mA plus the power dissipat ion of the CCLK

output driver, which is a function of the pin’s loading capac-

itance. CCLK is typically 1 MHz.

The primary s ource of static power dissipation i s not the

core array, but t he SRAM conf igur ation circu itry. It ha s tw o

blocks which consume static power – a pow er su pply volt -

age monitor and an internal oscillator. The voltage monitor

is used to initiate reboot when V

is first applied or when

goes below a c ritical voltage. T he monitor can not be

disabled. The internal oscillator can be turned off by setting

the B5 bit in the configuration register. With B5 set, the

AT6005 dissipates less than 900 µA static power (Table 1).

Power consumption calculation is performed automatically

by the Integrated Design System.

Table 1. AT6005 Static Power Dissipation

Min Typ Max

CC1

Modes 1, 2, 3, 6

Measured after reboot

2 mA

CC1

Modes 4, 5

With 50p load on CCLK

5 mA

CC2

Modes 1, 2, 3, 4, 5, 6

B5 Bit set with CONN = CSN = V

900 µA