1 Introduction
This document describes the estimated product lifetimes for the i.MX RT1010
applications processors based on the criteria used in the qualification process.
The product lifetimes described here are estimates and do not represent a
guaranteed lifetime of the processor.
The i.MX RT series consist of an extensive number of processors that
deliver a wide range of processing and multimedia capabilities across various
qualification levels.
This document guides on how to interpret different i.MX RT1010 qualification
levels in terms of the target operating frequency of the device, the maximum
supported junction temperature (Tj) of the processor, and how this relates to
the lifetime of the device.
Each qualification level supported, commercial and industrial, defines a number of Power-on Hours (PoH) available to the
processor under a given set of conditions, such as:
• The target frequency for the application, commercial and industrial.
— The target frequency is determined by the input voltage to the processor’s core complex (VDD_SOC_IN).
— The use of the DCDC-enabled or DCDC-bypass modes.
— When using the DCDC-bypass mode, the target voltage should not be set to the minimum specified in the datasheet.
All power management ICs have allowable tolerances. The target voltage must be set higher than the minimum
specified voltage to account for the tolerance of the PMIC. The tolerance assumed in the calculations in this
document is +/25 mV.
— The DCDC-enabled mode uses the DCDC module to create a power supply for the core logic on the i.MX RT series.
The DCDC module is well characterized and can be set to output the exact minimum specified voltage. Longer
Power-on-Hours can be achieved using the DCDC-enabled mode.
• The percentage of active use compared to standby.
— Active use means that the processor is running in an active performance mode.
— For the commercial tiers, there are two performance modes available: 500 MHz and 400 MHz.
— In the DSM mode, the datasheet defines lower operating conditions for VDD_SOC_IN, reducing the power
consumption and junction temperature. In this mode, the voltage and temperature are set low enough so that the
effect on the lifetime calculations is negligible and treated as if the device was powered off.
• The junction temperature (Tj) of the processor.
— The maximum junction temperature of the device is different for each tier of the product. For example, 95 ℃ for
commercial and 105 ℃ for industrial. This maximum temperature is guaranteed by the final test.
Ensure that your device is appropriately thermally managed and the maximum junction temperature is not exceeded.
Contents
1 Introduction......................................1
2 Device qualification level and
available PoH.................................. 2
2.1 Commercial qualification..............2
2.2 Industrial qualification.................. 4
3 Combining use cases......................6
3.1 Scenario 1: Switching between two
power states with different
voltages........................................6
3.2 Scenario 2: Switching between two
power states with different
temperatures................................7
3.3 Scenario 3: Using three or more
power states.................................8
AN13025
i.MXRT1010 Product Lifetime Usage Estimates
Rev. 0 — 10/2020
Application Note
All data provided within this document are estimates for the PoH that are based on extensive qualification
experience and testing with the i.MX RT series. These statistically derived estimates must not be viewed as a limit
on an individual device’s lifetime, nor construed as a guarantee by NXP as to the actual lifetime of the device. The
sales and warranty terms and conditions still apply.
NOTE
2 Device qualification level and available PoH
2.1 Commercial qualification
Table 1 provides the number of PoH for the typical use conditions for the commercial device.
Table 1. Commercial qualification lifetime estimates
— Arm
®
core speed
(MHz)
Power-on Hours
[PoH] (Hrs)
Arm core operating
voltage (V)
Junction temperature
[Tj] (℃)
Case C1: DCDC Enabled 500 28,098 1.25 95
Case C2: DCDC Enabled 400 76,379 1.15 95
Case C3: DCDC Bypassed 500 21,883 1.275 95
Case C4: DCDC Bypassed 400 59,484 1.175 95
Figure 1 and Figure 2 establish the guidelines for estimating the PoH as a function of CPU frequency and junction temperature.
The PoH can be read directly off the charts below to determine the necessary trade-offs for the CPU frequency and junction
temperature to increase the estimated PoH of the device.
NXP Semiconductors
Device qualification level and available PoH
i.MXRT1010 Product Lifetime Usage Estimates, Rev. 0, 10/2020
Application Note 2 / 10