“Gallium Nitride Transistor Packaging Advances and Thermal Modeling”, Johan Strydom, Michael de Rooij, and Alex Lidow, EDN China, September 2012
Published in EDN China, September 2012
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Gallium Nitr ide Tr ansistor Packa ging
Advances and Thermal Modeling
Johan Strydom, Michael de Rooij, and Alex Lidow,
Efficient Power Conversion Corporation
Introduction
Gallium nitride-based transistor replacements for power MOSFETs have been widely
available for over three years [1]. In addition to superior conductivity, these new-
generation devices switch ten times faster than their aged silicon ancestors. The
superior characteristics enable not only many new applications but also create more
stringent requirements for packaging and thermal management. In this article, we
discuss the advantages and thermal challenges of using the high performance
enhance me nt mo de e GaN
®
FETs in Land Grid Array (LGA) packages in high power
density systems.
The Ideal Package
As low voltage silicon MOSFET performance has improved over the last number of
years, the lack of high performance packaging has become a significant limiting factor,
stimulating the development of such innovative packages as the DirectFET [2], and
PolarPAK [3]. This leads to the question, what are the key requirements of a high
perform ance packag e, and what is the “ideal” package?
Semiconductor devices are packaged in order to improve (a) robustness, (b) protection
from the env ir onme nt, and (c) ease of handling. At higher voltages, some packaging
may also be needed to meet voltage clearance and creepag e req ui r eme nts. Packag ing,
however, degrades performance compared to the bare semiconductor die by adding to
the manuf actur i ng cost s, increasing on-resistance, increasing inductance, increasing
size, and degrading ther mal perfor manc e.
“Gallium Nitride Transistor Packaging Advances and Thermal Modeling”, Johan Strydom, Michael de Rooij, and Alex Lidow, EDN China, September 2012
What sets hi gh performance packaging apart is their ability to realize the required
advantages of device packaging while minimizing the drawbacks. At operating voltages
below about 200 V, leadless, dual-side-cooled packaging such as DirectFET, PolarPAK,
chip scale, or LGA becomes an elegant solution. Here the choice is largely dictated by
the devi ce’s terminal structure; vertical vs. lateral. A lateral device lends itself to easy
chip scale packaging (e. g. Great Wall’s BGA MOS FET s [4]), while a vertical, “flipped”
device needs to bring the high current substrate terminal down to the printed circuit
board (such as DirectFET or PolarPAK). In a si mil ar fashio n, EPC ’s eGaN devices are
in LGA packag es (see Figure 1) where the interdigitation of source and drain terminals
is used to minimiz e both on-resistance and parasitic inductance.
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