XAPP1159 (v1.0) January 21, 2013 www.xilinx.com 1
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Summary As systems become more complex and designers are asked to do more with less, FPGA
adaptability has become a critical asset. While Xilinx
®
FPGAs have always provided the
flexibility to do on-site device reprogramming, today's tougher cost, board space, and power
consumption constraints demand even more efficient design strategies.
Xilinx partial reconfiguration (PR) extends the inherent flexibility of the FPGA by allowing
specific regions of the FPGA to be reprogrammed with new functionality while applications
continue to run in the remainder of the device. Partial reconfiguration offers the following key
advantages over traditional full configuration:
• Reduced hardware resource utilization: the designer can fit more logic into an existing
device by dynamically time-multiplexing functions of the design
• Increased productivity and scalability: only the modified function needs to be implemented
in context with the already-verified remainder of the design
• Enhanced maintainability and reduced system down-time: new functions can be deployed
and inserted dynamically while the system is up and running
This application note describes the tool flow, concepts and techniques for using partial
reconfiguration on Xilinx Zynq™-7000 All Programmable SoC devices through the device
configuration (DevC) / processor configuration access port (PCAP) interface. The provided
reference design is built on top of the ZC702 Base Targeted Reference Design (TRD) [Ref 1],
an embedded video processing application that demonstrates the benefits of offloading a
compute-intensive video filter algorithm from software onto Programmable Logic. The design
demonstrates how to use software-controlled partial reconfiguration to dynamically reconfigure
part of the logic with one of two video filter IP cores and observe the video output on a monitor.
Introduction The Zynq-7000 AP SoC integrates a dual-core ARM Cortex-A9 based processing system (PS)
and programmable logic (PL) in a single device. This reference design makes use of both PS
and PL portions and demonstrates how it is best to separate control (mapped onto the PS) and
data path (mapped onto the PL). The PL implements a powerful, high-definition video pipeline
that consists of input, pre-processing, core processing, post-processing, and output stages
(see Figure 1). The PS is used to configure the individual IP cores inside the PL and to control
the data flow. The provided reference design offers the user to choose between a bare-metal
software application and two different Linux OS-based software applications running on the PS.
The ZC702 Base TRD [Ref 1] demonstrates the value of offloading a compute-intensive edge
detection algorithm (Sobel filter) onto the PL. The benefits are two-fold: (1) achieving real-time
processing of a 1080p60 video stream due to hardware acceleration and (2) freeing up CPU
resources for user-specific tasks such as rendering a graphical user interface (GUI) on top of
the processed video stream.
Application Note: Zynq-7000 All Programmable SoC
XAPP1159 (v1.0) January 21, 2013
Partial Reconfiguration of a Hardware
Accelerator on Zynq-7000 All Programmable
SoC Devices
Author: Christian Kohn
System Overview
XAPP1159 (v1.0) January 21, 2013 www.xilinx.com 2
Based on the ZC702 Base TRD, this application note describes the methodology of
implementing two different video processing accelerators in the PL by using partial
reconfiguration to load the desired functionality on demand. The first video filter IP core is a
Sobel filter that detects and displays the edges in the input video stream; the second video filter
IP core is a Sepia filter that applies a unique brown-tinted monochrome color to the input video
stream. Figure 2 shows a comparison of original, Sobel-processed, and Sepia-processed
images. The RTL for both video filter IP cores are generated from a C-algorithm description
using the High-Level Synthesis tool Vivado™ HLS. For details on the Sobel filter algorithm,
Vivado HLS tool flow, Linux device driver, and system integration, refer to XAPP890, Zynq All
Programmable SoC Sobel Filter Implementation Using the Vivado HLS Tool [Ref 2]. Similar
concepts can be applied to the provided Sepia filter example.
This application note assumes that the user is familiar with the ZC702 Base TRD [Ref 1] and its
hardware and software components. The focus of this work is to provide guidance on:
• Identifying functions that can benefit from partial reconfiguration
• Design considerations and interface requirements for reconfigurable modules
• Step-by-step partial reconfiguration design flow
• Implementing software-controlled partial reconfiguration through the PS DevC/PCAP
interface
System
Overview
This section gives a system-level overview of the Programmable Logic (PL) and the Processing
System (PS) of the provided reference design. Figure 3 shows the corresponding block
diagram.
X-Ref Target - Figure 1
Figure 1: Video Processing Pipeline
Input
Interface
Pre
Processing
Output
Interface
Core
Processing
Frame Buffers
DDR3 Memory
Frame Buffers
Post
Processing
Source
Sink
CPU
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X-Ref Target - Figure 2
Figure 2: Original Image (Left), Sobel-Processed Image (Center), Sepia-Processed Image (Right)
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