DS940 (v1.0) April 28, 2017 www.xilinx.com
Product Specification 1
Summary
The Zynq®-7000 All Programmable SoC
Verification Intellectual Property (VIP) supports the
functional simulation of Zynq-7000 based
applications. It is targeted to enable the functional
verification of Programmable Logic (PL) by
mimicking the Processor System (PS)-PL interfaces
and OCM/DDR memories of PS logic. This VIP is
delivered as a package of System Verilog modules.
VIP operation is controlled by using a sequence of
Verilog tasks contained in a Verilog-syntax file.
Features
• Pin compatible and Verilog-based simulation
model.
• Supports all AXI interfaces.
• AXI 3.0 compliant.
• 32/64–bit Data-width for AXI_HP, 32-bit for
AXI_GP and 64-bit for AXI_ACP.
• Sparse memory model (for DDR) and a RAM
model (for OCM).
• System Verilog task-based API.
• Delivered in Vivado® Design Suite.
• Blocking and non-blocking interrupt support.
• ID width support as per the Zynq-7000
specification.
• Support for FIXED, INCR and WRAP transaction
types.
• Support for all Zynq-7000 supported burst
lengths and burst sizes.
• Protocol checking, provided by the AXI VIP
models.
• Read/Write request capabilities.
• System Address Decode for OCM/DDR
transactions.
Zynq-7000 All Programmable SoC
Verification IP v1.0
DS940 (v1.0) April 28, 2017
Product Specification
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device Family
(1)
Zynq®-7000 All Programmable SoC, 7 Series
Supported User
Interfaces
AXI4, AXI4-Lite, AXI3
Resources Not Provided
Provided with Core
Design Files Not Provided
Example Design
Verilog
Test Bench
N/A
Constraints File
N/A
Simulation
Model
Verilog
Supported
S/W Driver
(2)
N/A
Tested Design Flows
(2)
Design Entry Vivado® Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
.
Synthesis Vivado synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
.
Zynq-7000 All Programmable SoC Verification IP v1.0
DS940 (v1.0) April 28, 2017 www.xilinx.com
Product Specification 2
Additional Features
• System Address Decode for Register Map Read transactions (only default value of the registers can be read).
• Support for static remap for AXI_GP0 and AXI_GP1.
• Configurable latency for Read/Write responses.
• First-level arbitration scheme based on the priority indicated by the AXI QoS signals.
• Datapath connectivity between any AXI master in PL and the PS memories and register map.
• Parameters to enable and configure AXI Master and Slave ports.
• APIs to set the traffic profile and latencies for different AXI Master and Slave ports.
• Support for FPGA logic clock generation.
• Soft Reset Control for the PL.
• API support to pre-load the memories, read/wait for the interrupts from PL, and checks for certain data
pattern to be updated at certain memory location.
• All unused interface signals that output to the PL are tied to a valid value.
• Semantic checks on all other unused interface signals.
An example design that demonstrates the usage of this VIP is available for reference.
Limitations
The following features are not yet supported by Zynq7000 APSoC VIP:
• Exclusive Access transfers are not supported on any of the slave ports.
• Read/Write data interleaving is not supported.
• Write access to the Register Map is not supported.
• Support for in-order transactions only.
Applications
The Zynq-7000 VIP is used to provide a simulation environment for the Zynq-7000 PS logic, typically
replacing the processing_system7 block in a design. The Zynq-7000 VIP models the following:
• Transactions originating from PS masters through the AXI VIP master API calls
• Transactions terminating through the PS slaves to models of the OCM and DDR memories through
interconnect models FCLK reset and clocking support
• Input interrupts to the PS from PL
• PS register map