WP434 (v1.2) October 29, 2015 www.xilinx.com 1
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Breakthrough system performance, unprecedented capacity,
and low power requirements make Xilinx® UltraScale™
devices the clear choice for many next-generation
applications.
White Paper: UltraScale Architecture
WP434 (v1.2) October 29, 2015
Xilinx UltraScale Architecture
for High-Performance,
Smarter Systems
By: Nick Mehta
Whether enabling a metropolitan area to communicate reliably, taking and
sending high-resolution medical images, or watching the latest blockbuster
from the comfort of home, the world has an ever-increasing, seemingly
insatiable demand for intelligent bandwidth. Systems are required to receive,
buffer, process, and transmit increasing quantities of data at faster data rates
while operating within strict power and fiscal budgets.
Xilinx is enabling system OEMs to meet these demands with enhanced silicon
capabilities in Kintex® UltraScale™ and Virtex® UltraScale devices, based on
the industry's first ASIC-class programmable architecture: the Xilinx UltraScale
architecture. Designed to scale from 20 nm planar technology through 16 nm
FinFET and beyond, the UltraScale architecture combines a successful
architectural platform with numerous innovative architectural developments
and second-generation 3D IC technology. Co-optimized with the Vivado®
Design Suite to provide higher device utilization and improved user
productivity, the UltraScale architecture enables users to build smarter systems
with fewer devices…faster.
WP434 (v1.2) October 29, 2015 www.xilinx.com 2
Xilinx UltraScale Architecture for High-Performance, Smarter Systems
MARKET CHALLENGES AND TRENDS
Many markets and applications require a tremendous increase in system bandwidth and processing
capability. Wired networking solutions are increasing from multiple links at 100 Gb/s through
400 Gb/s and up to 1 Tb/s; digital video applications are ramping from 1080p through 4K (Quad
HD) and up to 8K (Super Hi-Vision); wireless networks are moving from 3G through LTE Advanced
to NxN LTE Advanced. The increased data throughput requirements by all these different
applications end with the same result: increasing traffic and demands on all system components
(see in Figure 1).
As system bandwidth increases, demands upon the components within the system also increase.
More data needs to be transported between system components with increased buffering and data
processing requirements. Resulting data buses can commonly range from 512-bit to 2,048-bit,
putting strain on existing architectures. Xilinx UltraScale FPGAs address these issues with multiple
architectural enhancements and innovations, starting with the routing, clocking, and logic
structures.
X-Ref Target - Figure 1
Figure 1: Global IP Traffic Forecast from Cisco VNI for 2011–2016
110 EB
2016
WP434_01_102813
87 EB
2015
69 EB
2014
55 EB
2013
43 EB
2012
Exabytes per Month
Global IP Traffic Forecast from Cisco VNI for 2011–2016
31 EB
2011