WP419 (v1.0) March 27, 2012 www.xilinx.com 1
© Copy right 2012 Xilinx, Inc. Xilinx, t he Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated b rands included herein are trademarks of Xilinx in the Un ited
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The appetite for data is exploding, and the industry
is being forced to transition from parallel to serial
interface technology at constantly increasing speeds.
Higher data rates produce higher bandwidths and
present new demands and challenges in transceiver
design.
Serial systems today require very low bit-error rates.
As the serial signaling rate increases, channel-driven
signal distortion increases with it, while the bit
sampling time needed to process this distortion only
grows shorter. The techniques used to compensate
for signal distortion, therefore, become critical
elements in the design.
This compensation is usually called emphasis in the
transmit domain and equalization in the receive
domain. The effective implementation of emphasis
and equalization in Xilinx® 7 series FPGAs and
Zynq™-7000 Extensible Processing Platform (EPP) is
the subject of this white paper.
White Paper: 7 Series FPGAs
WP419 (v1.0) March 27, 2012
Equalization for High-Speed Serial
Interfaces in Xilinx 7 Series FPGA
Transceivers
By: Harry Fu
2 www.xilinx.com WP419 (v1.0) March 27, 2012
7 Series Transceiver Emphasis/Equalization Overview
7 Series Transceiver Emphasis/Equalization Overview
The Xilinx 7 series FPGA and EPP portfolios are based on the concept of a scalable,
optimized architecture, which allows all the FPGA elements to be scaled and
optimized to the market and target application. This yields the flexibility required to
port design investments to the “right fit” platform, based on current needs. The serial
transceivers are no exception. Xilinx offers a portfolio of transceivers that run from
500 Mb/s up to 28.05 Gb/s. See Figure 1.
This scalable approach enables cost-effective solutions for consumer applications,
where transceivers are used at lower data rates, to the very powerful, sophisticated
transceivers required by the telecommunications equipment used to move data
around the world.
Figure 2 depicts an example 2 x 100GE line card with traffic manager design showing
three different uses of 7 series serial transceivers.
X-Ref Target - Figure 1
Figure 1: Xilinx 7 Series FPGA Tran sceiver Portfolio
WP419_01_032012
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5
10
15
20
25
30
GTZ GTH
GTX GTP
28.05
13.1
12.5
6.6
Max Line RAte (Gb/s)
Transceivers