WP445 (v1.0) January 20, 2014 www.xilinx.com 1
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This white paper describes the capabilities of Xilinx®
7 series All Programmable FPGAs and SoCs to
implement high-clock-rate signal processing
functionality typically used by the datapath of
digital radio applications.
A clock rate higher than 500 MHz can be supported
on a mid-speed grade 7 series device with almost
100% of the logic slices, more than 90% of the DSP48
slices, and 70% of the block RAMs utilized. This
requires the designer to follow some rather simple
design rules that cover both algorithmic and
implementation aspects. These rules are reviewed in
the paper.
Although almost 100% of the slices can be used at
500 MHz for pure datapath designs, only 75% to 80%
of the logic resources (LUTs) are effectively occupied,
which essentially relates to routing and control set
resource constraints. A higher LUT utilization ratio
is achievable with the next-generation 20 nm
UltraScale™ architecture, which provides
significantly increased capabilities.
White Paper: All Programmable FPGAs and SoCs
WP445 (v1.0) January 20, 2014
Enabling High-Speed Radio Designs with
Xilinx All Programmable FPGAs and SoCs
By: Michel Pecot
2 www.xilinx.com WP445 (v1.0) January 20, 2014
Introduction
Introduction
Radio units are the most numerous components of a typical wireless network
deployment. Consequently, they contribute greatly to the total cost and power
consumption of the system. The contribution becomes even more significant with the
introduction of small cells and cloud Radio Access Networks (RANs), together with
the requirements for multi-mode and multi-Radio Access Technology (RAT) support
over larger bandwidths (up to 100 MHz and more), and a greater number of antennas.
To respond to these ever demanding requirements from network operators, radio
equipment vendors are continually innovating to improve the capabilities and
efficiency of their systems. New technologies have emerged over the past several
years for power amplifiers (e.g., digital Doherty, switched mode, and envelope
tracking techniques) and antenna systems (e.g., active antennas, multi-band solutions,
full-duplex networks), which are starting to be extensively deployed in the field.
These advanced techniques significantly increase the computational complexity of
digital signal processing algorithms, especially for functions like crest factor reduction
(CFR) or digital pre-distortion (DPD), but also require much higher levels of flexibility,
programmability, and integration. The Xilinx All Programmable FPGA and SoC
technology, which is based on a configurable fabric, is ideally suited to meet these
challenges. It is also very attractive because it offers a number of high-speed
transceivers and flexible I/Os, which can provide the physical interfaces necessary for
any digital radio solution (interfaces to baseband, DAC/ADC, and analog
components), while the FPGA logic can implement virtually any interfacing solution
(CPRI, JESD204B, etc.), as well as potential complementary switching functionality.
Built upon the 28 nm High-Performance Low-Power process technology (HPL), the
Xilinx Kintex®-7 FPGAs and Zynq®-7000 All Programmable SoCs (AP SoCs)
[Ref 1][Ref 2][Ref 3] deliver the required level of signal processing performance to
integrate complex digital radio applications. These devices also offer a significant
power advantage over: previous technology nodes, competing solutions using the
28 nm HP process, and even the 28 nm LP process. Power is an important
performance metric for such applications since it allows better thermal dissipation
while also providing cost savings on power supply components.
Zynq-7000 AP SoCs[Ref 3] are ideal for the integration of digital radio systems. Based
on the same programmable logic (PL) as the Kintex-7 FPGAs, the Zynq-7000 AP SoC
also integrates a complete processor system (PS) built around a dual-core ARM
®
Cortex™-A9 CPU tightly coupled with the PL. This architecture enables the
implementation of custom logic in the PL and custom software in the PS, facilitating
the realization of unique, differentiated system functions. The levels of performance
provided by this SoC implementation simply cannot be matched by any two-device
solution due to limited I/O bandwidth, higher latency, and/or higher power budget.
The integration of PL with a complete PS is of particular interest to those designing
radio applications. One ARM Cortex-A9 processor can support the OA&M and
board-level control functionality, running an RTOS such as Linux; the second core,
running bare metal, can execute DSP software, such as CFR/DPD coefficient
estimation (potentially complemented with some hardware acceleration in the PL),
while the PL implements the signal processing datapath.
To provide cost-effective solutions, it is necessary to fully exploit the capabilities of the
FPGA fabric, and architect the required functionality for the highest possible clock
rate. This indeed minimizes the application footprint, but also brings some benefit to
system power consumption.