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The Leader in High Temperature
Semiconductor Solutions
CHT-ADC10 Datasheet
High-Temperature Ultra-low-power 10-bit ADC
General Description
The CHT-ADC10 is a high-temperature,
ultra-low-power, highly stable analog-to-
digital converter. This successive approxi-
mation ADC is based on an R-2R network
and features 10 bits of resolution and a
strictly monotonic characteristic from -55°C
up to +225°C. An optional internal clock
generator is included to provide stand-
alone operation. It includes Sample&Hold
and µP interface with possibility of serial
data transfer. Both parallel and serial inter-
faces can be used simultaneously. A spe-
cial control line allows for doubling the fre-
quency of the internal clock generator for
reduced throughput time. The maximum
sampling rate is 25kS/s. Several input
ranges are available from -15V up to +10V.
It only requires a +5V supply and an exter-
nal +5V reference.
The CHT-ADC10 is latch-up free and the
fabrication technology guarantees a high
reliability at extreme temperatures.
Features
• 10 bit-resolution with optional internal
clock, Sample/Hold, µC interface with
parallel or serial data transfer
• Up to 25kS/s
• +5V power supply only
• Low total supply current ( <250 µA)
• Operational from -55 to +225°C with
very low drift
• Validated at 225°C for 20000 hours (and
still on-going)
• Available in die, CDIL28 and CSOIC28
Applications
• Oil&Gas, Industrial, Automotive, Aero-
nautics & Aerospace
• Electric Power Conversion
Package Configurations
1
Vdd_D
10_n8
nCS
A0
R_nC
CE
CK
Gnd_D
Gnd_A
Vdd_A (Vref)
Ctrl_freq
Vin_bip
Vin_5
Vin_10
nEOC
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Dout
SCLK
Gnd_D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CHT-ADC10
1
Pinout is identical for CDIL28 and CSOIC28. Other packages available upon request.
Ordering Information
Ordering Reference
Package
Temperature Range
Marking
Status
CHT-ADC10-CDIL28-T
Ceramic DIL28
-55°C to +225°C
CHT-ADC10
Not for new design
CHT-ADC10-CSOIC28-T
Ceramic SOIC28
-55°C to +225°C
CHT-ADC10
Active
15-Feb-21 Contact : Gonzalo Picún (+32-10-489214)Feb. 21
CHT-ADC10 - DATASHEET
(Last Modification Date)
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Functional Block Diagram
Input
Sampling
400k
400k
200k
Control Logic
(10-bit successive approximation)
Gnd_DGnd_A
Vdd_DVdd_A
Par/Ser
Converter
Vin_5
Vin_10
Vin_bip
10_n8
10
10
nEOC
DOUT
CK
Detector
Internal
CK
CK
Selector
CK
SCLK
[D9..D0]
MSB LSB
A0
R_nC
CE
nCS
Pin Description
Pin#
Symbol
Type
1
Function
1
Vdd_D
SD
+5V digital supply (+/- 5%).
2
10_n8
DI
Determines whether output data is
to be organized as two 8-bit words
(low) or a single 10-bit word
(high).
3
nCS
DI
(active low) Chip Select.
4
A0
DI
During the read cycle, if 10_n8 is
low, A0 low enables the 8 MSBs
(D9…D2) while A0 high enables
(D1,D0) and sets (D7…D2)=0.
5
R_nC
DI
Read/Convert. Active high for
Read and low for write.
6
CE
DI
(active high) Chip Enable.
7
CK
DI
Optional clock input. Must be
grounded if not used. If used,
should preferably be high during
12µs after the starting of conver-
sion for noise reasons. Range:
10kHz and 500kHz ; duty-
cycle:10% to 90%.
8
Gnd_D
SD
Digital ground.
9
Gnd_A
SA
Analog ground.
10
Vdd_A
(Vref)
SA
Analog supply voltage. It is also
used as internal voltage refer-
ence. Must be a precise and
noiseless 5V supply (current
<200µA). The accuracy of this
reference directly affects the ADC
gain error.
11
Ctrl_
freq
DI
Should be high for normal opera-
tion. If low, it doubles the internal
oscillator frequency (~500kHz) at
cost of a lower precision.
12
Vin_bip
AI
Analog signal input. It is connect-
ed to an internal 400k resistor.
See Static Characteristics table
for possible input ranges.
1
Type: S=Supply, A=Analog; D=Digital; I=input;
O=output
Pin#
Symbol
Type
1
Function
13
Vin_5
AI
Analog signal input. It is connect-
ed to an internal 200k resistor.
See Static Characteristics table
for possible input ranges.
14
Vin_10
AI
Analog signal input. It is connect-
ed to an internal 400k resistor.
See Static Characteristics table
for possible input ranges.
15
Gnd_D
SD
Digital ground.
16
SCLK
DI
Must be low whilst CS is active
with a conversion in progress.
After End-of-Conversion, each
SCLK falling edge shifts data out
through DOUT. Maximum SCLK
frequency is 10MHz.
17
Dout
DO
Tri-state serial data output. When
nCS is high, Dout is in high-
impedance state. When nCS is
low, Dout is low during conversion
and goes high at end of conver-
sion. After this rising edge, new
data (starting from MSB) go out at
each falling edge of SCLK.
18
D0 (LSB)
DO
Tri-state parallel data output.
19
D1
DO
20
D2
DO
21
D3
DO
22
D4
DO
23
D5
DO
24
D6
DO
25
D7
DO
26
D8
DO
27
D9(MSB)
DO
28
nEOC
DO
Represents the End-of-
Conversion (active low) flag.