© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 5
1 Publication Order Number:
NB4N527S/D
NB4N527S
Translator, 3.3 V, 2.5 Gb/s
Dual AnyLevel & trade; to
LVDS Receiver/Driver/
Buffer, with Internal
Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevel
TM
input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will r
eceive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to V
CC
− 50 mV combined with two 50 W internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
• Maximum Input Clock Frequency up to 1.5 GHz
• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
• 470 ps Maximum Propagation Delay\
• 1 ps Maximum RMS Jitter
• 140 ps Maximum Rise/Fall Times
• Single Power Supply; V
CC
= 3.3 V $10%
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• Internal 50 W Termination Resistor per Input Pin
• GND + 50 mV to V
CC
− 50 mV V
CMR
Range
• These are Pb−Free Devices
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2
23−1
(V
INPP
= 400 mV; Input Signal DDJ = 14 ps)
VOLTAGE (130 mV/div)
Device DDJ = 10 ps
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN−16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
16
NB4N
527S
ALYW G
G
1
Q0
Q0
Figure 1. Functional Block Diagram
VTD0
D0
Q1
Q1
D0
50 W*
D1
D1
VTD0
50 W*
50 W*
50 W*
VTD1
VTD1
1
*R
TIN
(Note: Microdot may be in either location)
NB4N527S
http://onsemi.com
2
Figure 3. Pin Configuration (Top View)
GND NC NC V
CC
VTD0 D0 D0 VTD0
Q0
Q0
Q1
Q1
V
TD1
D1
D1
V
TD1
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB4N527S
Exposed Pad (EP)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTD1 −
Internal 50 W termination pin for D1. (R
TIN
)
2 D1 LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D1 input (Note 1).
3 D1 LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D1 input (Note 1).
4 VTD1 −
Internal 50 W termination pin for D1. (R
TIN
)
5 GND − 0 V. Ground.
6, 7 NC No connect.
8 V
CC
Positive Supply Voltage.
9 Q1 LVDS Output
Inverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10 Q1 LVDS Output
Noninverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
11 Q0 LVDS Output
Inverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
12 Q0 LVDS Output
Noninverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
13 VTD0 −
Internal 50 W termination pin for D0.
14 D0 LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D0 input (Note 1).
15 D0 LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D0 input (Note 1).
16 VTD0 −
Internal 50 W termination pin for D0.
EP Exposed pad. EP on the package bottom is thermally connected to the die
improved heat transfer out of package. The pad is not electrically connected
to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0
, D1/D1 input, then the device will be susceptible to self−oscillation.