The MRAM is designed for very high
reliability. Redundant write control lines,
error correction coding and low-voltage
write protection ensure the correct
operation of the memory and protection
from inadvertent writes.
Integrated Power Up and Power Down
circuitry controls the condition of the
device during power transitions. It is
fabricated with Honeywell’s radiation
hardened Silicon On Insulator (SOI)
technology, and is designed for use in
low-voltage systems operating in radiation
environments. The MRAM operates over
a temperature range of -40°C to +105°C
and is operated with 3.3 ± 0.3V and
1.8 ± 0.15V power supplies.
HXNV0100
HXNV0100 1Megabit
64K x 16 Non-Volatile Magneto-Resistive RAM
Features
n Fabricated on S150 Silicon On
Insulator (SOI) CMOS Underlayer
Technology
n 150 nm Process
n
n
Total Dose Hardness 3x10
5
and
n Dose Rate Survivability 1x10
12
rad(Si)/s
n Soft Error Rate 1x10
-10
upsets/bit-day
n Neutron Hardness 1x10
14
N/cm
2
n No Latchup
n Read Access Time 80 ns
n Read Cycle Time 110 ns
n Write Cycle Time 140 ns
n Unlimited Read (> 1x10
15
Cycles)
n 15 years Data Retention
n Synchronous Operation
n Single-Bit Error Detection &
Correction (ECC)
n Dual Power Supplies
n 1.8 V ± 0.15V, 3.3 V ± 0.3V
n 3.3V CMOS Compatible I/O
n Standard Operating Temperature
Range is -40°C to +105°C
n Package: 64 Lead Shielded
Ceramic Quad Flat Pack
The Honeywell 1 Megabit radiation hardened low power non-volatile Magneto-Resistive
Random Access Memory (MRAM) oers high performance and is designed for space
and military applications. The part is congured as a 65,536 word x 16 bit MRAM.
PRODUCTION - Release - 15 Sep 2014 08:29:12 MST - Printed on 15 Sep 2014
1x10
6
rad (Si)
Dose Rate Upset Hardness 1x10
9
rad(Si)/s
Simplied Functional
Block Diagram
Signal Description
Signal Denition
A(15:0) A(15) is MSB, A(0) is LSB.
DQ(15:0)
Data Input/Output Signals. Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation.
CS Chip select. Rising edge initiates an access of memory. A(15:0), WE and DQ(15:0) are latched on the rising edge. High level required for DQ(15:0)
outputs to be enabled.
WE Write Enable. Active high write enable. High state at rising edge of CS initiates a write cycle. Low state at rising edge of CS initiates a read cycle.
OE Output Enable. Active high output enable. Low state puts outputs in high impedance state.
NWI0 Not Write Inhibit – When set low, these signals inhibit writes to the memory. A high level allows the memory to be written.
NWI1 NWI0 controls lower order 32K A(15)=0.
NWI1 controls the upper order 32K A(15)=1.
(Note the VIL and VIH requirements for NWI)
TESTOUT This pin shall be treated as a “no connect” and have no connection on the circuit board.
TESTIN1 These signals are for Honeywell test purposes only. These must be grounded. (Failure to hold these pins low may result in
TESTIN2 permanent loss of functionality)
TESTIN3
TESTIN4
VDD1 DC Power Source Input: nominal 1.8V
VDD2 DC Power Source Input: nominal 3.3V
2
D
C
Q
D
C
Q
D
C
Q
D
C
Q
Digit Line Drivers
Bit Line Drivers
A(0:6)
OE
NWI
WE
CS
A(7:15)
DQ(0:15)
Row
Decoder
Data Array
65,536 x 16
ECC Array
65,536 x 5
ECC Logic
Column Decoder
Data Input/Output
Read Circuit