SX1231H

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ADVANCED COMMUNICATIONS & SENSING DATASHEET

SX1231H Transceiver

Low Power Integrated UHF Transceiver with On-Chip +20dBm PA

Rev 1 - Oct 2011

The SX1231H is a highly integrated RF transceiver capable

of operation over a wide frequency range, including the 433,

868 and 915 MHz license-free ISM (Industry Scientific and

Medical) frequency bands. Its highly integrated architecture

allows for a minimum of external components whilst

maintaining maximum design flexibility. All major RF

communication parameters are programmable and most of

them can be dynamically set. The SX1231H offers the

unique advantage of programmable narrow-band and wide-

band communication modes without the need to modify

external components. The SX1231H is optimized for low

power consumption while offering high RF output power and

channelized operation. TrueRF™ technology enables a low-

cost external component count (elimination of the SAW

filter) whilst still satisfying ETSI and FCC regulations.

 Automated Meter Reading

 Wireless Sensor Networks

 Home and Building Automation

 Wireless Alarm and Security Systems

 Industrial Monitoring and Control

 Wireless M-BUS

 Europe: EN 300-220-1

 North America: FCC Part 15.247, 15.249, 15.231

 +20 dBm - 100 mW Power Output Capability

 High Sensitivity: down to -120 dBm at 1.2 kbps

 High Selectivity: 16-tap FIR Channel Filter

 Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,

80 dB Blocking Immunity, no Image Frequency response

 Low current: Rx = 16 mA, 100nA register retention

 Programmable Pout: -18 to +20 dBm in 1dB steps

 Constant RF performance over voltage range of chip

 FSK Bit rates up to 300 kb/s

 Fully integrated synthesizer with a resolution of 61 Hz

 FSK, GFSK, MSK, GMSK and OOK modulations

 Built-in Bit Synchronizer performing Clock Recovery

 Incoming Sync Word Recognition

 115 dB+ Dynamic Range RSSI

 Automatic RF Sense with ultra-fast AFC

 Packet engine with CRC-16, AES-128, 66-byte FIFO

 Built-in temperature sensor

 QFN 24 Package - Operating Range [-40;+85°C]

 Pb-free, Halogen free, RoHS/WEEE compliant product

GENERAL DESCRIPTION

APPLICATIONS

MARKETS

KEY PRODUCT FEATURES

ORDERING INFORMATION

Part Number Delivery MOQ / Multiple

SX1231HIMLTRT Tape & Reel

3000 pieces

LNA

Single to

Differential

Mixers

Σ/Δ

Modulators

Decimation and

& Filtering

Demodulator &

Bit Synchronizer

Interpolation

& Filtering

Modulator

Packet Engine & 66 Bytes FIFO

Control Registers - Shift Registers - SPI Interface

SPI

DIO0

RSSI AFC

Division by

2, 4 or 6

Frac-N PLL

Synthesizer

32 MHz

XTAL

PA0

PA1&2

Tank

Inductor

Loop

Filter

RFIO

PA_BOOST

RESET

Power Distribution System

VBAT1&2 VR_ANA VR_DIG

VR_PA

Ramp &

Control

Oscillator

GND

RXTX

GND

DIO1

DIO2

DIO3

DIO4

DIO5

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SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

Rev 1 - Oct 2011

Table of Contents Page

1. General Description ................................................................................................................................................ 8

1.1. Simplified Block Diagram ................................................................................................................................ 8

1.2. Pin and Marking Diagram................................................................................................................................ 9

1.3. Pin Description .............................................................................................................................................. 10

2. Electrical Characteristics....................................................................................................................................... 11

2.1. ESD Notice.................................................................................................................................................... 11

2.2. Absolute Maximum Ratings .......................................................................................................................... 11

2.3. Operating Range........................................................................................................................................... 11

2.4. Chip Specification ......................................................................................................................................... 12

2.4.1. Power Consumption ................................................................................................................................. 12

2.4.2. Frequency Synthesis ................................................................................................................................ 12

2.4.3. Receiver ................................................................................................................................................... 13

2.4.4. Transmitter ............................................................................................................................................... 14

2.4.5. Digital Specification ...................................................................................................................................15

3. Chip Description.................................................................................................................................................... 16

3.1. Power Supply Strategy.................................................................................................................................. 16

3.2. Frequency Synthesis..................................................................................................................................... 16

3.2.1. Reference Oscillator ................................................................................................................................. 16

3.2.2. CLKOUT Output ........................................................................................................................................17

3.2.3. PLL Architecture ....................................................................................................................................... 17

3.2.4. Lock Time .................................................................................................................................................. 18

3.2.5. Lock Detect Indicator................................................................................................................................ 18

3.3. Transmitter Description ................................................................................................................................. 19

3.3.1. Architecture Description ........................................................................................................................... 19

3.3.2. Bit Rate Setting ........................................................................................................................................ 19

3.3.3. FSK Modulation ........................................................................................................................................ 20

3.3.4. OOK Modulation....................................................................................................................................... 20

3.3.5. Modulation Shaping.................................................................................................................................. 21

3.3.6. Power Amplifiers ...................................................................................................................................... 21

3.3.7. High Power Settings ..................................................................................................................................22

3.3.8. Output Power Summary ........................................................................................................................... 22

3.3.9. Over Current Protection ........................................................................................................................... 22

3.4. Receiver Description ..................................................................................................................................... 23

3.4.1. Block Diagram .......................................................................................................................................... 23

3.4.2. LNA - Single to Differential Buffer ............................................................................................................ 23

3.4.3. Automatic Gain Control ............................................................................................................................ 24

3.4.4. Continuous-Time DAGC........................................................................................................................... 25

3.4.5. Quadrature Mixer - ADCs - Decimators.................................................................................................... 26

3.4.6. Channel Filter ........................................................................................................................................... 26

3.4.7. DC Cancellation ....................................................................................................................................... 27