Si5381/82 Rev. E Reference Manual
Overview
This Reference Manual is intended to provide system, PCB design, signal integrity, and
software engineers the necessary technical information to successfully use the
Si5381/82 devices in end applications. The official device specifications can be found in
the Si5381/82 datasheet.
The Si5381/82 is a high performance jitter attenuating clock multiplier which integrates
four/two any-frequency DSPLLs for applications that require maximum integration and in-
dependent timing paths. A single low phase noise XO connected to the XA/XB input pins
provides the reference for the device. The device supports ultra-low phase noise 4G/LTE
clock generation and low jitter general-purpose clock synthesis from a single device.
Each DSPLL has access to any of the four inputs and can provide low jitter clocks on
any of the device outputs. Based on fourth generation DSPLL technology, these devices
provide any-frequency conversion with typical jitter performance under 100 fs (4G/LTE
frequency outputs). Each DSPLL supports independent Free Run, holdover modes of
operation, as well as automatic and hitless input clock switching. The Si5381/82 is pro-
grammable via an SPI or I
2
C serial interface with in-circuit programmable non-volatile
memory so that it always powers up in a known configuration.
RELATED DOCUMENTS
• Si5381/82 Data Sheet
• Si5381/82 Device Errata
•
Si5381/82A-E-EVB User Guide
• Si5381/82A-E-EVB Schematics, BOM &
Layout
• IBIS models
• To download evaluation board design and
support files, go to:
• https://www.silabs.com/development-
tools/timing/jitter-attenuator/si5382-
evaluation-kit
• https://www.silabs.com/development-
tools/timing/jitter-attenuator/si5381-
evaluation-kit
• JESD204B subclass 0 and subclass 1
support
Work Flow Expectations with ClockBuilder
™
Pro and the Register Map
This reference
manual is to be used to describe all the functions and features of the parts in the product family with register map details
on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder
™
Pro software to pro-
vide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a
valid and optimum frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency
plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose
of this document. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how
to implement the most common, real-time frequency plan changes.
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Table of Contents
1. Functional Description............................
5
1.1 DSPLL.................................5
1.2 Si5381/82 LTE Frequency Configuration .....................7
1.3 Si5381/82 Configuration for JESD204B Subclass 1 Clock Generation ...........8
1.4 DSPLL Loop Bandwidth ...........................9
1.4.1 Fastlock ...............................10
1.4.2 Holdover Exit Bandwidth .........................10
1.5 Dividers Overview .............................11
2. Modes of Operation ............................12
2.1 Reset and Initialization ...........................13
2.1.1 Updating Registers During Device Operation ..................14
2.1.2 NVM Programming ...........................15
2.2 Free Run Mode ..............................15
2.3 Lock Acquisition Mode ...........................15
2.4 Locked Mode ..............................15
2.5 Holdover Mode ..............................16
2.6 VCO Freeze Mode.............................18
3. Clock Inputs (IN0, IN1, IN2, IN3/FB_IN) .....................19
3.1 Input Source Selection ...........................20
3.1.1 Manual Input Selection ..........................21
3.1.2 Automatic Input Switching .........................22
3.2 Types of Inputs ..............................22
3.2.1 Hitless Input Switching ..........................24
3.2.2 Use Case Scenario: Using More Than Two Inputs ................25
3.2.3 Ramped Input Switching .........................26
3.2.4 Glitchless Input Switching .........................26
3.2.5 Unused Inputs.............................26
3.2.6 Slew Rate Considerations .........................27
3.3 Fault Monitoring .............................28
3.3.1 Input LOS (Loss-of-Signal) Detection .....................28
3.3.2 XAXB Reference Clock LOSXAXB (Loss-of-Signal) Detection ............29
3.3.3 Input OOF (Out-of-Frequency) Detection ....................30
3.3.4 DSPLL Loss-of-Lock (LOL) Detection .....................32
3.3.5 Device Status Monitoring .........................34
3.3.6 INTRb Interrupt Configuration .......................36
4. Output Clocks ..............................38
4.1 Output Crosspoint Switch ..........................38
4.1.1 Output R Divider Synchronization ......................39
4.2 Performance Guidelines for Outputs .......................40
4.2.1 Optimizing Output Phase Noise for Si5381/82 ..................41
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